Whitelist v7 feature for ARM and AARCH64.

[gnzlbg]

Needed for v7 features in coresimd.

See https://github.com/rust-lang-nursery/stdsimd/blob/b2f7be24d5043a88427f9a5258ca9a51ede6d029/coresimd/src/arm/v7.rs#L40 which used to work but doesn't anymore.

r? alexcrichton

[rust-highfive]

r? @nikomatsakis

(rust_highfive has picked a reviewer for you, use r? to override)

[gnzlbg]

r? @alexcrichton

[alexcrichton]

@bors: r+ rollup

[bors]

📌 Commit b32dbbc has been approved by alexcrichton

[Amanieu]

Why was the v7 feature added to AArch64? There is no v7 LLVM feature for AArch64 since it is assumed to always be available. I think this should be removed from the AArch64 list.

[gnzlbg]

What should:

#[target_feature(enabled = "v7")] unsafe fn foo() {}

do on AArch64? If the v7 feature is not whitelisted, at least with the current system, this should fail to compile. EDIT: Those targeting both AArch64 and ARM would need to write:

#[cfg_attr(target_arch = "arm", target_feature(enabled = "v7")]
unsafe fn foo() {}

[Amanieu]

It should fail to compile. You should use #[cfg_attr(target_arch = "arm", target_feature(enabled = "v7")] instead: enable v7 on ARM, no-op on AArch64.

[gnzlbg]

I would be fine with that, but the original reason this was white-listed was for code that works on ARM to work on AArch64 "as is", without modifications.

[gnzlbg]

If this is an issue, probably this should be made consistent for x86 as well. There are many features in x86_64 that are enabled by default on top of x86 (sse, sse2, ...). @alexcrichton that would mean that writing #[target_feature(enable = "sse")] on x86_64 would need to become an error.

[Amanieu]

I don't think this really makes sense for ARM. x86 and x86_64 are practically identical instruction sets and share the same features. However ARM and AArch64 are effectively completely different instruction sets, and have very different feature lists.

[gnzlbg]

Isn't AArch64 a super-set of ARM ? All the ARM intrinsics that we have currently implemented are available on AArch64 as well (same name, same llvm intrinsic name, same assembly instruction name, etc.).

[BubbaSheen]

So exactly what is the issue with this coding?? Asking strictly out of curiosity.

[gnzlbg]

IIUC the problem is that v7 is not a feature that can be enabled / disabled on AArch64, so it does not make much sense to have it as such.

[Amanieu]

Isn't AArch64 a super-set of ARM ? All the ARM intrinsics that we have currently implemented are available on AArch64 as well.

This is only actually true for the NEON intrinsics. Many of the remaining intrinsics are only available in the 32-bit instruction set, e.g. DSP (__smlabb), integer saturation (__ssat), 32-bit SIMD (__sadd8, int8x4_t)...

[gnzlbg]

This is only actually true for the NEON intrinsics.

The bit manipulation intrinsics (rbit and friends) are not part of neon and IIRC and are available on both.