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Add the Cortex-M7 TCM and cache access control registers. #352
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Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @thalesfragoso (or someone else) soon. Please see the contribution instructions for more information. |
This sounds like an example of where a feature in the processor core isn't tied to an architecture (e.g. We already have a feature flag for |
I have added a generic |
These registers appear to specific to the Cortex-M7, so add a feature gate "cm7".
Friendly "ping" on this @adamgreig or @thejpster, if anyone has a moment spare. |
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Thanks for the ping. All the values check out, looks good.
bors merge
Build succeeded: |
375: Prepare v0.7.4 r=thejpster a=adamgreig I've created a new branch, `v0.7.x`, which is currently at the latest non-breaking commit (so includes #346 #349 #347 #351 #339 #352 #348 #363 #362 #361 but does not include #342), to track the 0.7 series since master now contains breaking changes for v0.8. This PR (which targets the new branch) cherry-picks #372 #369 #374 and bumps the version to v0.7.4 (and updates CHANGELOG) ready for a new v0.7.4 release. Once complete I'll also backport the changelog entries and bump the version in master to 0.7.4. I think this is everything that should be in 0.7 -- the only excluded PRs from master are #342 and #367 I believe, and I don't think we have any open PRs targeting 0.7 either. Any other thoughts on items for inclusion in 0.7.4 (or other changelog entries I missed)? Co-authored-by: bors[bot] <26634292+bors[bot]@users.noreply.github.com> Co-authored-by: Adam Greig <[email protected]>
Add the Cortex-M7 TCM and cache access control registers.
These are documented in the Cortex-M7 generic user guide (ARM DUI 0646C).
I'm not sure what feature gate these should be on - should I add a new one for Cortex-M7? Currently I have them on
not(armv6m)
- they do not appear to be in the ARMv7M architecture documentation, so I presume they are M7 specific.