Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add the Cortex-M7 TCM and cache access control registers. #352

Merged
merged 1 commit into from
Sep 23, 2021
Merged

Add the Cortex-M7 TCM and cache access control registers. #352

merged 1 commit into from
Sep 23, 2021

Conversation

rcls
Copy link
Contributor

@rcls rcls commented Sep 5, 2021

Add the Cortex-M7 TCM and cache access control registers.

These are documented in the Cortex-M7 generic user guide (ARM DUI 0646C).

I'm not sure what feature gate these should be on - should I add a new one for Cortex-M7? Currently I have them on not(armv6m) - they do not appear to be in the ARMv7M architecture documentation, so I presume they are M7 specific.

@rust-highfive
Copy link

Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @thalesfragoso (or someone else) soon.

Please see the contribution instructions for more information.

@rust-highfive rust-highfive added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-cortex-m labels Sep 5, 2021
@thejpster
Copy link
Contributor

This sounds like an example of where a feature in the processor core isn't tied to an architecture (e.g. armv7e-m) but instead to a specific processor design. As far as the Arm Armv7-M ARM is concerned, TCM is either "implementation defined" or "not available".

We already have a feature flag for cm7-r0p1 to work around a specific silicon bug. Adding one for cm7-tcm doesn't seen unreasonable. Or just a generic cm7 flag if the TCM function applies to all Cortex-M7 cores (where cm7-r0p1 would depend on cm7).

@rcls
Copy link
Contributor Author

rcls commented Sep 5, 2021

Or just a generic cm7 flag if the TCM function applies to all Cortex-M7 cores

I have added a generic cm7 flag. (Looking closely, there are a few register bits, e.g., the AXIM async bus fault, that appear to apply to all CM7s, not just those with TCM & caches.)

These registers appear to specific to the Cortex-M7, so add a feature gate
"cm7".
@rcls
Copy link
Contributor Author

rcls commented Sep 13, 2021

Friendly "ping" on this @adamgreig or @thejpster, if anyone has a moment spare.

Copy link
Member

@adamgreig adamgreig left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks for the ping. All the values check out, looks good.

bors merge

@bors
Copy link
Contributor

bors bot commented Sep 23, 2021

Build succeeded:

@bors bors bot merged commit 9e9ab9a into rust-embedded:master Sep 23, 2021
@adamgreig adamgreig mentioned this pull request Dec 31, 2021
bors bot added a commit that referenced this pull request Jan 2, 2022
375: Prepare v0.7.4 r=thejpster a=adamgreig

I've created a new branch, `v0.7.x`, which is currently at the latest non-breaking commit (so includes #346 #349 #347 #351 #339 #352 #348 #363 #362 #361 but does not include #342), to track the 0.7 series since master now contains breaking changes for v0.8.

This PR (which targets the new branch) cherry-picks #372 #369 #374 and bumps the version to v0.7.4 (and updates CHANGELOG) ready for a new v0.7.4 release. Once complete I'll also backport the changelog entries and bump the version in master to 0.7.4.

I think this is everything that should be in 0.7 -- the only excluded PRs from master are #342 and #367 I believe, and I don't think we have any open PRs targeting 0.7 either.

Any other thoughts on items for inclusion in 0.7.4 (or other changelog entries I missed)?

Co-authored-by: bors[bot] <26634292+bors[bot]@users.noreply.github.com>
Co-authored-by: Adam Greig <[email protected]>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-cortex-m
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants