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Merged
merged 3 commits into from
Jan 11, 2020
Merged

Coreir operator inlining #523

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09fd404
Update gold files for bit const codegen
leonardt Jan 6, 2020
c0ae983
Merge branch 'master' into coreir-verilog-inline
leonardt Jan 11, 2020
0fa2900
Update golds
leonardt Jan 11, 2020
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30 changes: 15 additions & 15 deletions tests/test_syntax/gold/ArrayOfBitsSeq.v
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Original file line number Diff line number Diff line change
Expand Up @@ -91,21 +91,21 @@ wire [1023:0] reg_PR_inst7_out;
wire [1023:0] reg_PR_inst8_out;
wire [1023:0] reg_PR_inst9_out;
ArrayOfBitsSeq_comb ArrayOfBitsSeq_comb_inst0(.I_0(I_0), .I_1(I_1), .I_10(I_10), .I_11(I_11), .I_12(I_12), .I_13(I_13), .I_14(I_14), .I_2(I_2), .I_3(I_3), .I_4(I_4), .I_5(I_5), .I_6(I_6), .I_7(I_7), .I_8(I_8), .I_9(I_9), .O0_0(ArrayOfBitsSeq_comb_inst0_O0_0), .O0_1(ArrayOfBitsSeq_comb_inst0_O0_1), .O0_10(ArrayOfBitsSeq_comb_inst0_O0_10), .O0_11(ArrayOfBitsSeq_comb_inst0_O0_11), .O0_12(ArrayOfBitsSeq_comb_inst0_O0_12), .O0_13(ArrayOfBitsSeq_comb_inst0_O0_13), .O0_14(ArrayOfBitsSeq_comb_inst0_O0_14), .O0_2(ArrayOfBitsSeq_comb_inst0_O0_2), .O0_3(ArrayOfBitsSeq_comb_inst0_O0_3), .O0_4(ArrayOfBitsSeq_comb_inst0_O0_4), .O0_5(ArrayOfBitsSeq_comb_inst0_O0_5), .O0_6(ArrayOfBitsSeq_comb_inst0_O0_6), .O0_7(ArrayOfBitsSeq_comb_inst0_O0_7), .O0_8(ArrayOfBitsSeq_comb_inst0_O0_8), .O0_9(ArrayOfBitsSeq_comb_inst0_O0_9), .O1_0(ArrayOfBitsSeq_comb_inst0_O1_0), .O1_1(ArrayOfBitsSeq_comb_inst0_O1_1), .O1_10(ArrayOfBitsSeq_comb_inst0_O1_10), .O1_11(ArrayOfBitsSeq_comb_inst0_O1_11), .O1_12(ArrayOfBitsSeq_comb_inst0_O1_12), .O1_13(ArrayOfBitsSeq_comb_inst0_O1_13), .O1_14(ArrayOfBitsSeq_comb_inst0_O1_14), .O1_2(ArrayOfBitsSeq_comb_inst0_O1_2), .O1_3(ArrayOfBitsSeq_comb_inst0_O1_3), .O1_4(ArrayOfBitsSeq_comb_inst0_O1_4), .O1_5(ArrayOfBitsSeq_comb_inst0_O1_5), .O1_6(ArrayOfBitsSeq_comb_inst0_O1_6), .O1_7(ArrayOfBitsSeq_comb_inst0_O1_7), .O1_8(ArrayOfBitsSeq_comb_inst0_O1_8), .O1_9(ArrayOfBitsSeq_comb_inst0_O1_9), .self_register_array_O_0(reg_PR_inst0_out), .self_register_array_O_1(reg_PR_inst1_out), .self_register_array_O_10(reg_PR_inst10_out), .self_register_array_O_11(reg_PR_inst11_out), .self_register_array_O_12(reg_PR_inst12_out), .self_register_array_O_13(reg_PR_inst13_out), .self_register_array_O_14(reg_PR_inst14_out), .self_register_array_O_2(reg_PR_inst2_out), .self_register_array_O_3(reg_PR_inst3_out), .self_register_array_O_4(reg_PR_inst4_out), .self_register_array_O_5(reg_PR_inst5_out), .self_register_array_O_6(reg_PR_inst6_out), .self_register_array_O_7(reg_PR_inst7_out), .self_register_array_O_8(reg_PR_inst8_out), .self_register_array_O_9(reg_PR_inst9_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_0), .out(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_1), .out(reg_PR_inst1_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst10(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_10), .out(reg_PR_inst10_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst11(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_11), .out(reg_PR_inst11_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst12(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_12), .out(reg_PR_inst12_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst13(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_13), .out(reg_PR_inst13_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst14(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_14), .out(reg_PR_inst14_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst2(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_2), .out(reg_PR_inst2_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst3(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_3), .out(reg_PR_inst3_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst4(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_4), .out(reg_PR_inst4_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst5(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_5), .out(reg_PR_inst5_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst6(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_6), .out(reg_PR_inst6_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst7(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_7), .out(reg_PR_inst7_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst8(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_8), .out(reg_PR_inst8_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst9(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_9), .out(reg_PR_inst9_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_0), .out(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_1), .out(reg_PR_inst1_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst10(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_10), .out(reg_PR_inst10_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst11(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_11), .out(reg_PR_inst11_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst12(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_12), .out(reg_PR_inst12_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst13(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_13), .out(reg_PR_inst13_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst14(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_14), .out(reg_PR_inst14_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst2(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_2), .out(reg_PR_inst2_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst3(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_3), .out(reg_PR_inst3_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst4(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_4), .out(reg_PR_inst4_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst5(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_5), .out(reg_PR_inst5_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst6(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_6), .out(reg_PR_inst6_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst7(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_7), .out(reg_PR_inst7_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst8(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_8), .out(reg_PR_inst8_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst9(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_9), .out(reg_PR_inst9_out));
assign O_0 = ArrayOfBitsSeq_comb_inst0_O1_0;
assign O_1 = ArrayOfBitsSeq_comb_inst0_O1_1;
assign O_10 = ArrayOfBitsSeq_comb_inst0_O1_10;
Expand Down
4 changes: 2 additions & 2 deletions tests/test_syntax/gold/CustomEnv.v
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Expand Up @@ -24,8 +24,8 @@ wire [1:0] TestBasic_comb_inst0_O2;
wire [1:0] reg_PR_inst0_out;
wire [1:0] reg_PR_inst1_out;
TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_PR_inst0_out), .self_y_O(reg_PR_inst1_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h2), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h2), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out));
assign O = TestBasic_comb_inst0_O2;
endmodule

2 changes: 1 addition & 1 deletion tests/test_syntax/gold/RdPtr.v
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Expand Up @@ -36,7 +36,7 @@ wire [9:0] RdPtr_comb_inst0_O0;
wire [9:0] RdPtr_comb_inst0_O1;
wire [9:0] reg_PR_inst0_out;
RdPtr_comb RdPtr_comb_inst0(.O0(RdPtr_comb_inst0_O0), .O1(RdPtr_comb_inst0_O1), .read(read), .self_rd_ptr_O(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(10'h000), .width(10)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(RdPtr_comb_inst0_O0), .out(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(10'h000), .width(10)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(RdPtr_comb_inst0_O0), .out(reg_PR_inst0_out));
assign O = RdPtr_comb_inst0_O1;
endmodule

6 changes: 3 additions & 3 deletions tests/test_syntax/gold/RegisterMode.v
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ wire [3:0] Register_comb_inst0_O0;
wire [3:0] Register_comb_inst0_O1;
wire [3:0] reg_P_inst0_out;
Register_comb Register_comb_inst0(.O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .en(en), .self_value_O(reg_P_inst0_out), .value(value));
coreir_reg #(.clk_posedge(1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out));
coreir_reg #(.clk_posedge(1'b1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out));
assign O = Register_comb_inst0_O1;
endmodule

Expand Down Expand Up @@ -121,8 +121,8 @@ Mux2xOutBits4 Mux2xOutBits4_inst6(.I0(value), .I1(value), .O(Mux2xOutBits4_inst6
Mux2xOutBits4 Mux2xOutBits4_inst7(.I0(self_register_O), .I1(value), .O(Mux2xOutBits4_inst7_O), .S(magma_Bits_2_eq_inst8_out));
Mux2xOutBits4 Mux2xOutBits4_inst8(.I0(self_register_O), .I1(self_register_O), .O(Mux2xOutBits4_inst8_O), .S(magma_Bits_2_eq_inst9_out));
Mux2xOutBits4 Mux2xOutBits4_inst9(.I0(Mux2xOutBits4_inst6_O), .I1(value), .O(Mux2xOutBits4_inst9_O), .S(magma_Bits_2_eq_inst10_out));
corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out));
corebit_const #(.value(1)) bit_const_1_None(.out(bit_const_1_None_out));
corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
corebit_const #(.value(1'b1)) bit_const_1_None(.out(bit_const_1_None_out));
coreir_const #(.value(2'h0), .width(2)) const_0_2(.out(const_0_2_out));
coreir_const #(.value(2'h1), .width(2)) const_1_2(.out(const_1_2_out));
corebit_not magma_Bit_not_inst0(.in(magma_Bit_xor_inst0_out), .out(magma_Bit_not_inst0_out));
Expand Down
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