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Port Map
This page includes the hardware port map for:
The hardware supports a logical address space of 4MB comprising 256x16K memory pages. The 16bit/64K address space is split into 4x16K blocks. Any of the 256 pages can be mapped into any of the 4 physical address blocks. The base CPU card comprises 512K of flash and 512K of static RAM, 32 pages each. After power-on/reset the hardware page select is disabled and (usually*) the first four pages of Flash memory are mapped into the Z80 address space.
NOTE * There is a jumper on the card to select whether Flash or SRAM is mapped to the Z80 after a reset. I previously used the SRAM first and used a Raspberry Pi to take control of the bus and write code directly into the RAM. I don't use this now that I've enough software and a Flash programmer!
NOTE after a reset memory paging is disabled. This usually means the first 64K of Flash memory is mapped into the Z80 memory map. The ZLoader code copies itself to RAM, enables memory paging and maps RAM into the Z80 address space.
NOTE these registers are write only. There's no mechanism to read the currently configured memory pages.
| Port | Description |
|---|---|
| 60h | Page to map to the first 16K block of Z80 physical memory (block 0) |
| 61h | Page to map to the second 16K block of Z80 physical memory (block 1) |
| 62h | Page to map to the third 16K block of Z80 physical memory (block 2) |
| 63h | Page to map to the fourth 16K block of Z80 physical memory (block 3) |
| Bit | Description |
|---|---|
| 0 | controls whether page mapping is enabled. It is not after a reset. Writing 1 to this port enables block mapping into memory pages. Be careful not to reset this bit when changing other bits in this register (2) |
| 1 | i2c data output |
| 2 | SDCard 1 select (SPI_S1) and LED1 (SDCard 1) |
| 3 | SDCard 2 select (SPI_S2) and LED2 (SDCard 2) |
| 4 | SPI_S3/LED3 - uncommitted SPI device select |
| 5 | SPI_S4/LED4 - uncommitted SPI device select |
| 6 | SPI_S5/LED5 - uncommitted SPI device select |
NOTE 1: The i2c clock is wired to A0. To write out a single bit to the i2c interface first write to bit 1 on port 64h and then write the same value to port 65h. This will transition the i2c clock and stroke a single bit.
NOTE 2: If using paged memory then be very careful NOT to inadvertently write '0' to this bit when programming i2C or SPI controls. Doing so will disable the page registers and map flash back into the CPU memory.
| Bit | Name | Description |
|---|---|---|
| 0 | MISO | Input data bit for the SPI interface |
| 1 | i2cDA | Input data bit for the i2c interface |
| 2 | i2cCL | Input value of the i2c clock |
| 3 | CARD1 | High if SDCard 1 contains an SDCard (see below) |
| 4 | CARD2 | High if SDCard 2 contains an SDCard (see below) |
| 5 | DIP0 | DIP Switch bit 0 |
| 6 | DIP1 | DIP Switch bit 1 |
| 7 | DIP2 | DIP Switch bit 2 |
NOTE: If the SDCard adaptor is NOT present then the CARDx signals will also be high. There's no way to distinguish between adaptor missing or adaptor present and card installed. Generally there should always be an adaptor inserted into the SDCard 0 slot.
Both port 68h and 69h reference the same output port and controls the SPI output. Writing to port 68h sets the data line with the SPI_CLK line low. Writing to port 69h sets the data line with the clock high. To strobe data out write to port 68h then the same data to port 69h. This will set the data and toggle the clock line.
| Bit | Description |
|---|---|
| 0 | SPI data line |
For details on programming this device reference the Z80 Peripheral User Manual.
| Port | Description |
|---|---|
| 40h | CTC Channel 0 (and interrupt vector) |
| 41h | CTC Channel 1 |
| 42h | CTC Channel 2 |
| 43h | CTC Channel 3 |
CTC channel 0 can be used to generate a variable baud rate for the two channels of the SIO. P6 selects clock input for channel 0 and P3 for channel 1.
CTC channel 3 is used by ZLoader to run time orientated tasks. At the time of writing the timer is used to periodically scan the Omega MSX keyboard if installed and to 'blink' the cursor on the text VDU card.
The SIO contains two serial controllers named port A and port B. Each has a control and a data register. See the SIO data sheet for details or the Z80 Peripheral User Manual for programming details.
| Port | Description |
|---|---|
| 80h | SIO port B data register |
| 81h | SIO port A data register |
| 82h | SIO port B control register |
| 83h | SIO port A control register |
The video card has a single input and single output port. This hardware was going to be used to interface with the Omega MSX keyboard however after testing the video card it was determined that the processor really needed to be able to read the VSYNC signal from the hardware in order to deliver smooth video. As such bit 7 of the input port got 'wired' from the VSYNC signal. This is yet to be reflected in the schamtics and PCB. As such the port was not then suitable for the keyboard interface, which was moved to the PIO/keyboard card.
An 8 bit generic, latched output port. Write the value to this port and the output lines will be driven.
The matching 8 bit input port. Bit 7 of this should be patched to accept the signal for VSync (Pin 17 of U6).
The PIO card is still under test and subject to change. This add-on card includes:
- Z80 PIO - which can be used in a 'raw' mode or (port 1) as a dual joystick interface
- A keyboard interface designed to connect to the Omega MSX design's keyboard
- A SN76489 sound chip with output to drive headphones or a small 8 ohm speaker
| Port | Description |
|---|---|
| C0h | PIO port A data register |
| C1h | PIO port B data register |
| C2h | PIO port A control register |
| C3h | PIO port B control register |
The keyboard is accessed through port C4 which operates as both a latched output and an 8 bit 'column' input.
| Bit | Description |
|---|---|
| 3-0 | Row number. The keyboard is a matrix. Select a row then read the column to get switch states (2) |
| 4 | Keyboard 'CAPS' LED |
| 5 | Keyboard 'Fn1' LED |
| 6 | PIO card LED control |
| 7 | Input select control (1) |
Notes
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The input select control changes the data that appears on the
COL0input line. If this bit is set to zero then theCOL0input reflects theColumn 0value from the MSX keyboard. If it is set to one then ARDY line from the SN76489 sound chip. Polling this bit allows the processor to determine when the sound chip is ready to receive more data (the sounds chip is very slow). -
The Omega MSX keyboard is a fairly simple matrix. There are 9 rows, each row contains 8 switches. The processor can read the state of all switches in one row by writing a row number (0-9) to bits 0-3 of port 64h (which is latched) and then reading the value of the 8 switches by reading from port 64h. Please bear in mind note 1 above for the column 0 status. To see the layout of the keys on the keyboard, refer to the Omega MSX keyboard schematic
Write data to the SN76489 sound chip. Writes to the sound chip are very slow. Before writing to the sound chip, first read the ARDY value from port C4h (see note 1 above for port C4h about readying ARDY rather than keyboard status).
To understand how to programme the sound card reference the SN76489 data sheet.