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Bug 1669938 - Promote pseudo-min/max wasm SIMD instructions to accept…
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…ed status. r=jseward

Background: WebAssembly/simd#122

For all the pseudo-min/max SIMD instructions:

- remove the internal 'Experimental' opcode suffix in the C++ code
- remove the guard on experimental Wasm instructions in all the C++ decoders
- move the test cases from simd/experimental.js to simd/ad-hack.js

I have checked that current V8 and wasm-tools use the same opcode
mappings.  V8 in turn guarantees the correct mapping for LLVM and
binaryen.

Differential Revision: https://phabricator.services.mozilla.com/D92928
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Lars T Hansen committed Oct 14, 2020
1 parent 49c0d8a commit 5ee6736
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Showing 9 changed files with 32 additions and 69 deletions.
7 changes: 7 additions & 0 deletions js/src/jit-test/tests/wasm/simd/ad-hack.js
Original file line number Diff line number Diff line change
Expand Up @@ -588,6 +588,9 @@ function min_u(bits) {
}
}

function pmin(x, y) { return y < x ? y : x }
function pmax(x, y) { return x < y ? y : x }

assertEq(max_s(8)(1, 2), 2);
assertEq(max_s(8)(1, 128), 1);
assertEq(min_s(8)(1, 2), 1);
Expand Down Expand Up @@ -689,6 +692,10 @@ for ( let [op, memtype, rop, resultmemtype] of
['f64x2.gt', Float64Array, gt(-1), BigInt64Array],
['f64x2.le', Float64Array, le(-1), BigInt64Array],
['f64x2.ge', Float64Array, ge(-1), BigInt64Array],
['f32x4.pmin', Float32Array, pmin],
['f32x4.pmax', Float32Array, pmax],
['f64x2.pmin', Float64Array, pmin],
['f64x2.pmax', Float64Array, pmax],
])
{
let [ins, mem, resultmem] = insAndMemBinop(op, memtype, resultmemtype);
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36 changes: 0 additions & 36 deletions js/src/jit-test/tests/wasm/simd/experimental.js
Original file line number Diff line number Diff line change
Expand Up @@ -50,9 +50,6 @@ function iota(len) {
return xs;
}

function pmin(x, y) { return y < x ? y : x }
function pmax(x, y) { return x < y ? y : x }

const v2vSig = {args:[], ret:VoidCode};

function V128Load(addr) {
Expand All @@ -66,39 +63,6 @@ function V128StoreExpr(addr, v) {
SimdPrefix, V128StoreCode, 4, varU32(0)];
}

// Pseudo-min/max, https://github.com/WebAssembly/simd/pull/122
var fxs = [5, 1, -4, NaN];
var fys = [6, 0, -7, 3];
var dxs = [5, NaN];
var dys = [6, 0];

for ( let [opcode, xs, ys, operator] of [[F32x4PMinCode, fxs, fys, pmin],
[F32x4PMaxCode, fxs, fys, pmax],
[F64x2PMinCode, dxs, dys, pmin],
[F64x2PMaxCode, dxs, dys, pmax]] ) {
var k = xs.length;
var ans = iota(k).map((i) => operator(xs[i], ys[i]))

var ins = wasmEval(moduleWithSections([
sigSection([v2vSig]),
declSection([0]),
memorySection(1),
exportSection([{funcIndex: 0, name: "run"},
{memIndex: 0, name: "mem"}]),
bodySection([
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
...V128Load(32),
SimdPrefix, varU32(opcode)])]})])]));

var mem = new (k == 4 ? Float32Array : Float64Array)(ins.exports.mem.buffer);
set(mem, k, xs);
set(mem, 2*k, ys);
ins.exports.run();
var result = get(mem, 0, k);
assertSame(result, ans);
}

// Widening integer dot product, https://github.com/WebAssembly/simd/pull/127

var ins = wasmEval(moduleWithSections([
Expand Down
3 changes: 1 addition & 2 deletions js/src/jit/MacroAssembler.h
Original file line number Diff line number Diff line change
Expand Up @@ -2653,8 +2653,7 @@ class MacroAssembler : public MacroAssemblerSpecific {
inline void unsignedWidenLowInt32x4(FloatRegister src, FloatRegister dest)
DEFINED_ON(x86_shared, arm64);

// Compare-based minimum/maximum (experimental as of August, 2020)
// https://github.com/WebAssembly/simd/pull/122
// Compare-based minimum/maximum

inline void pseudoMinFloat32x4(FloatRegister rhs, FloatRegister lhsDest)
DEFINED_ON(x86_shared, arm64);
Expand Down
8 changes: 4 additions & 4 deletions js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2594,16 +2594,16 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
case wasm::SimdOp::F64x2Ge:
masm.compareFloat64x2(Assembler::GreaterThanOrEqual, rhs, lhsDest);
break;
case wasm::SimdOp::F32x4PMaxExperimental:
case wasm::SimdOp::F32x4PMax:
masm.pseudoMaxFloat32x4(rhs, lhsDest);
break;
case wasm::SimdOp::F32x4PMinExperimental:
case wasm::SimdOp::F32x4PMin:
masm.pseudoMinFloat32x4(rhs, lhsDest);
break;
case wasm::SimdOp::F64x2PMaxExperimental:
case wasm::SimdOp::F64x2PMax:
masm.pseudoMaxFloat64x2(rhs, lhsDest);
break;
case wasm::SimdOp::F64x2PMinExperimental:
case wasm::SimdOp::F64x2PMin:
masm.pseudoMinFloat64x2(rhs, lhsDest);
break;
case wasm::SimdOp::I32x4DotSI16x8Experimental:
Expand Down
12 changes: 4 additions & 8 deletions js/src/wasm/WasmBaselineCompile.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -14970,17 +14970,13 @@ bool BaseCompiler::emitBody() {
CHECK_NEXT(dispatchVectorBinary(NarrowUI32x4));
case uint32_t(SimdOp::V8x16Swizzle):
CHECK_NEXT(dispatchVectorBinary(Swizzle));
case uint32_t(SimdOp::F32x4PMaxExperimental):
CHECK_SIMD_EXPERIMENTAL();
case uint32_t(SimdOp::F32x4PMax):
CHECK_NEXT(dispatchVectorBinary(PMaxF32x4));
case uint32_t(SimdOp::F32x4PMinExperimental):
CHECK_SIMD_EXPERIMENTAL();
case uint32_t(SimdOp::F32x4PMin):
CHECK_NEXT(dispatchVectorBinary(PMinF32x4));
case uint32_t(SimdOp::F64x2PMaxExperimental):
CHECK_SIMD_EXPERIMENTAL();
case uint32_t(SimdOp::F64x2PMax):
CHECK_NEXT(dispatchVectorBinary(PMaxF64x2));
case uint32_t(SimdOp::F64x2PMinExperimental):
CHECK_SIMD_EXPERIMENTAL();
case uint32_t(SimdOp::F64x2PMin):
CHECK_NEXT(dispatchVectorBinary(PMinF64x2));
case uint32_t(SimdOp::I32x4DotSI16x8Experimental):
CHECK_SIMD_EXPERIMENTAL();
Expand Down
8 changes: 4 additions & 4 deletions js/src/wasm/WasmConstants.h
Original file line number Diff line number Diff line change
Expand Up @@ -660,8 +660,8 @@ enum class SimdOp {
F32x4Div = 0xe7,
F32x4Min = 0xe8,
F32x4Max = 0xe9,
F32x4PMinExperimental = 0xea,
F32x4PMaxExperimental = 0xeb,
F32x4PMin = 0xea,
F32x4PMax = 0xeb,
F64x2Abs = 0xec,
F64x2Neg = 0xed,
// Round = 0xee
Expand All @@ -672,8 +672,8 @@ enum class SimdOp {
F64x2Div = 0xf3,
F64x2Min = 0xf4,
F64x2Max = 0xf5,
F64x2PMinExperimental = 0xf6,
F64x2PMaxExperimental = 0xf7,
F64x2PMin = 0xf6,
F64x2PMax = 0xf7,
I32x4TruncSSatF32x4 = 0xf8,
I32x4TruncUSatF32x4 = 0xf9,
F32x4ConvertSI32x4 = 0xfa,
Expand Down
11 changes: 4 additions & 7 deletions js/src/wasm/WasmIonCompile.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4905,13 +4905,10 @@ static bool EmitBodyExprs(FunctionCompiler& f) {
case uint32_t(SimdOp::F64x2Le):
case uint32_t(SimdOp::F64x2Ge):
case uint32_t(SimdOp::V8x16Swizzle):
CHECK(
EmitBinarySimd128(f, /* commutative= */ false, SimdOp(op.b1)));
case uint32_t(SimdOp::F32x4PMaxExperimental):
case uint32_t(SimdOp::F32x4PMinExperimental):
case uint32_t(SimdOp::F64x2PMaxExperimental):
case uint32_t(SimdOp::F64x2PMinExperimental):
CHECK_SIMD_EXPERIMENTAL();
case uint32_t(SimdOp::F32x4PMax):
case uint32_t(SimdOp::F32x4PMin):
case uint32_t(SimdOp::F64x2PMax):
case uint32_t(SimdOp::F64x2PMin):
CHECK(
EmitBinarySimd128(f, /* commutative= */ false, SimdOp(op.b1)));
case uint32_t(SimdOp::I8x16Splat):
Expand Down
8 changes: 4 additions & 4 deletions js/src/wasm/WasmOpIter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -430,10 +430,10 @@ OpKind wasm::Classify(OpBytes op) {
case SimdOp::I16x8NarrowSI32x4:
case SimdOp::I16x8NarrowUI32x4:
case SimdOp::V8x16Swizzle:
case SimdOp::F32x4PMinExperimental:
case SimdOp::F32x4PMaxExperimental:
case SimdOp::F64x2PMinExperimental:
case SimdOp::F64x2PMaxExperimental:
case SimdOp::F32x4PMin:
case SimdOp::F32x4PMax:
case SimdOp::F64x2PMin:
case SimdOp::F64x2PMax:
case SimdOp::I32x4DotSI16x8Experimental:
WASM_SIMD_OP(OpKind::Binary);
case SimdOp::I8x16Neg:
Expand Down
8 changes: 4 additions & 4 deletions js/src/wasm/WasmValidate.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1052,12 +1052,12 @@ static bool DecodeFunctionBodyExprs(const ModuleEnvironment& env,
case uint32_t(SimdOp::I16x8NarrowSI32x4):
case uint32_t(SimdOp::I16x8NarrowUI32x4):
case uint32_t(SimdOp::V8x16Swizzle):
case uint32_t(SimdOp::F32x4PMax):
case uint32_t(SimdOp::F32x4PMin):
case uint32_t(SimdOp::F64x2PMax):
case uint32_t(SimdOp::F64x2PMin):
CHECK(iter.readBinary(ValType::V128, &nothing, &nothing));

case uint32_t(SimdOp::F32x4PMaxExperimental):
case uint32_t(SimdOp::F32x4PMinExperimental):
case uint32_t(SimdOp::F64x2PMaxExperimental):
case uint32_t(SimdOp::F64x2PMinExperimental):
case uint32_t(SimdOp::I32x4DotSI16x8Experimental):
CHECK_SIMD_EXPERIMENTAL();
CHECK(iter.readBinary(ValType::V128, &nothing, &nothing));
Expand Down

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