[stm32] RCC: Fix wrong PLL HSI source selection

[rleh]

On STM32F042 (and other STM32F0/STM32F3) Rcc::enablePll(Rcc::PllSource::InternalClock, pllFactors) selects the Hsi clock divided by 2 (and not divided by PllFactors::pllPrediv) as pll source.

enum class PllSource : uint32_t {
  /// High speed internal clock (8 MHz)
  Hsi = RCC_CFGR_PLLSRC_HSI_DIV2,
  InternalClock = Hsi,
  // [...]
}

#define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */

---

Related to #413

[rleh]

For more information see #413 (comment)

cc @nesos @salkinium

[rleh]

Seems like only some STM32F0 have the RCC_CFGR_PLLSRC_HSI_PREDIV option. 😒

The following devices do not have the pre-divider (according to CMSIS headers):

• stm32f030x6
• stm32f030x8
• stm32f031x6
• stm32f038xx
• stm32f051x8
• stm32f058xx

[rleh]

Maybe this problem is also related to #99 ?!

[salkinium]

Thanks!

[salkinium]

Why ST, whyyyyyyy?