Accelerate STM32 QSPI read/write operations by DMA

storage/filesystem/fat/source/FATFileSystem.cpp

@@ -155,7 +155,11 @@ extern "C" DWORD get_fattime(void)
 
 extern "C" void *ff_memalloc(UINT size)
 {
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    return aligned_alloc(__SCB_DCACHE_LINE_SIZE, size);
+#else
     return malloc(size);
+#endif
 }
 
 extern "C" void ff_memfree(void *p)

targets/TARGET_STM/TARGET_STM32F4/objects.h

@@ -28,6 +28,12 @@
 #include "stm32f4xx_ll_rtc.h"
 #include "stm32f4xx_ll_rcc.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -150,6 +156,11 @@ struct qspi_s {
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 

targets/TARGET_STM/TARGET_STM32F4/stm_dma_info.h

@@ -48,4 +48,9 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {2, 6, 1}, // SPI6 Rx is DMA2 Stream 6 Channel 1
 };
 
+/// Mapping from QSPI index to DMA link info
+static const DMALinkInfo QSPIDMALinks[] = {
+        {2, 7, 3}, // QUADSPI is DMA2 Stream 7 Channel 3
+};
+
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32F7/objects.h

@@ -42,6 +42,12 @@
 #include "stm32f7xx_ll_pwr.h"
 #include "stm32f7xx_ll_rcc.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -124,6 +130,11 @@ struct qspi_s {
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 

targets/TARGET_STM/TARGET_STM32F7/stm_dma_info.h

@@ -48,4 +48,9 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {2, 6, 1}, // SPI6 Rx is DMA2 Stream 6 Channel 1
 };
 
+/// Mapping from QSPI index to DMA link info
+static const DMALinkInfo QSPIDMALinks[] = {
+        {2, 7, 3}, // QUADSPI is DMA2 Stream 7 Channel 3
+};
+
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32G4/objects.h

@@ -26,6 +26,12 @@
 #include "stm32g4xx_ll_rtc.h"
 #include "stm32g4xx_ll_rcc.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -106,6 +112,11 @@ struct qspi_s {
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 

targets/TARGET_STM/TARGET_STM32G4/stm_dma_info.h

@@ -44,5 +44,11 @@ static const DMALinkInfo SPIRxDMALinks[] = {
 #endif
 };
 
+/// Mapping from QSPI index to DMA link info
+static const DMALinkInfo QSPIDMALinks[] = {
+#if defined(QUADSPI)
+        {1, 7, DMA_REQUEST_QUADSPI },
+#endif
+};
 
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32H7/objects.h

@@ -31,6 +31,12 @@
 #include "stm32h7xx_ll_pwr.h"
 #include "stm32h7xx_ll_system.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -84,6 +90,7 @@ struct analogin_s {
 struct qspi_s {
 #if defined(OCTOSPI1)
     OSPI_HandleTypeDef handle;
+    IRQn_Type qspiIRQ;
 #else
     QSPI_HandleTypeDef handle;
 #endif
@@ -94,12 +101,18 @@ struct qspi_s {
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 
 #if DEVICE_OSPI
 struct ospi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type ospiIRQ;
     OSPIName ospi;
     PinName io0;
     PinName io1;
@@ -112,6 +125,11 @@ struct ospi_s {
     PinName sclk;
     PinName ssel;
     PinName dqs;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 

targets/TARGET_STM/TARGET_STM32H7/stm_dma_info.h

@@ -42,5 +42,17 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {2, 0, DMA_REQUEST_SPI5_RX},
 };
 
+/// Mapping from QSPI/OSPI index to DMA link info
+#if defined(OCTOSPI1)
+static const DMALinkInfo OSPIDMALinks[] = {
+        {MDMA_IDX, 0, MDMA_REQUEST_OCTOSPI1_FIFO_TH},
+        {MDMA_IDX, 1, MDMA_REQUEST_OCTOSPI2_FIFO_TH}
+};
+#else
+static const DMALinkInfo QSPIDMALinks[] = {
+        {MDMA_IDX, 0, MDMA_REQUEST_QUADSPI_FIFO_TH},
+};
+#endif
+
 
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32L4/objects.h

@@ -31,6 +31,12 @@
 #include "stm32l4xx_ll_pwr.h"
 #include "stm32l4xx_ll_rcc.h"
 
+#include "stm_dma_utils.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -106,6 +112,7 @@ struct can_s {
 struct qspi_s {
 #if defined(OCTOSPI1)
     OSPI_HandleTypeDef handle;
+    IRQn_Type qspiIRQ;
 #else
     QSPI_HandleTypeDef handle;
 #endif
@@ -116,12 +123,18 @@ struct qspi_s {
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 
 #if DEVICE_OSPI
 struct ospi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type ospiIRQ;
     OSPIName ospi;
     PinName io0;
     PinName io1;
@@ -134,6 +147,11 @@ struct ospi_s {
     PinName sclk;
     PinName ssel;
     PinName dqs;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 #endif
 

targets/TARGET_STM/TARGET_STM32L4/stm_dma_info.h

@@ -40,6 +40,12 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {1, 6, DMA_REQUEST_SPI3_RX}
 };
 
+/// Mapping from OSPI index to DMA link info
+static const DMALinkInfo OSPIDMALinks[] = {
+        {1, 7, DMA_REQUEST_OCTOSPI1},
+        {2, 1, DMA_REQUEST_OCTOSPI2},
+};
+
 #else
 
 
@@ -60,6 +66,11 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {2, 1, 3}  // SPI3 Rx is DMA2 Ch1 Request 3
 };
 
+/// Mapping from QSPI index to DMA link info
+static const DMALinkInfo QSPIDMALinks[] = {
+        {2, 7, 3}, // QUADSPI is DMA2 Ch7 Request 3
+};
+
 #endif
 
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32L5/objects.h

@@ -27,6 +27,12 @@
 #include "stm32l5xx_ll_pwr.h"
 #include "stm32l5xx_ll_rcc.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -105,17 +111,24 @@ struct can_s {
 
 struct qspi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type qspiIRQ;
     QSPIName qspi;
     PinName io0;
     PinName io1;
     PinName io2;
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 
 struct ospi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type ospiIRQ;
     OSPIName ospi;
     PinName io0;
     PinName io1;
@@ -128,6 +141,11 @@ struct ospi_s {
     PinName sclk;
     PinName ssel;
     PinName dqs;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 
 #ifdef __cplusplus

targets/TARGET_STM/TARGET_STM32L5/stm_dma_info.h

@@ -38,5 +38,9 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {1, 6, DMA_REQUEST_SPI3_RX},
 };
 
+/// Mapping from OSPI index to DMA link info
+static const DMALinkInfo OSPIDMALinks[] = {
+        {1, 7, DMA_REQUEST_OCTOSPI1},
+};
 
 #endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32U5/objects.h

@@ -27,6 +27,12 @@
 #include "stm32u5xx_ll_pwr.h"
 #include "stm32u5xx_ll_rcc.h"
 
+#include "stm_dma_info.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#include "cmsis_os2.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -105,17 +111,24 @@ struct can_s {
 
 struct qspi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type qspiIRQ;
     QSPIName qspi;
     PinName io0;
     PinName io1;
     PinName io2;
     PinName io3;
     PinName sclk;
     PinName ssel;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 
 struct ospi_s {
     OSPI_HandleTypeDef handle;
+    IRQn_Type ospiIRQ;
     OSPIName ospi;
     PinName io0;
     PinName io1;
@@ -128,6 +141,11 @@ struct ospi_s {
     PinName sclk;
     PinName ssel;
     PinName dqs;
+    bool dmaInitialized;
+#if MBED_CONF_RTOS_PRESENT
+    osSemaphoreId_t semaphoreId;
+    osRtxSemaphore_t semaphoreMem;
+#endif
 };
 
 #ifdef __cplusplus

targets/TARGET_STM/TARGET_STM32U5/stm_dma_info.h

@@ -38,5 +38,12 @@ static const DMALinkInfo SPIRxDMALinks[] = {
         {1, 5, GPDMA1_REQUEST_SPI3_TX}
 };
 
+/// Mapping from OSPI index to DMA link info
+static const DMALinkInfo OSPIDMALinks[] = {
+        {1, 6, GPDMA1_REQUEST_OCTOSPI1},
+#if defined(OCTOSPI2)
+        {1, 7, GPDMA1_REQUEST_OCTOSPI2}
+#endif
+};
 
 #endif //MBED_OS_STM_DMA_INFO_H