kv: nvfp4_ds_mla — 4-bit NVFP4 KV cache for B12X sparse MLA (SM120) - #82
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lukealonso merged 2 commits intoJul 14, 2026
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Adds an opt-in "nvfp4_ds_mla" KV cache dtype for the B12X sparse-MLA backend: the 512-dim MLA latent is stored as packed NVFP4 (E2M1 data + per-16-group E4M3 scales) instead of fp8, shrinking the per-token record from 656 B to 432 B per layer (256 B FP4 NoPE + 32 B E4M3 scales + 16 B alignment pad + 128 B BF16 RoPE) for +39-48% KV pool at equal budget. Behavior is unchanged unless opted in: every change is gated on kv_cache_dtype == "nvfp4_ds_mla", and fp8_ds_mla serving takes byte-identical code paths — including the b12x call signatures. The scale_format / caps kwargs are forwarded to b12x ONLY for the FP4 record, so fp8 serving keeps working on a b12x tree without the nvfp4 read-path port. Write side: csrc concat_and_cache_nvfp4_mla, in-tree in libtorch_stable/cache_kernels.cu (+ ops.h decl, _C_cache_ops schema), guarded by ENABLE_NVFP4_SM100/SM120 with a clear error on pre-Blackwell builds. _custom_ops falls back to loading a companion vllm/_nvfp4_mla_cache_C.so iff the main build lacks the op, so the feature can also ship as an overlay on an existing image. Read side: requires the b12x ScaleFormat.NVFP4_E4M3 (== 2) decode/extend path (companion b12x PR to follow); until that lands, requesting nvfp4_ds_mla fails loudly at plan construction with an unexpected-kwarg error. B12X_MLA_SPARSE only; FLASHMLA_SPARSE still canonicalizes to fp8_ds_mla. Validated on GLM-5.2 753B @ TP4/DCP4 on 4x RTX PRO 6000 (SM120): KV pool 454,510 vs 307,547 tokens (+47.8%) at util 0.96; GPQA-Diamond 174/198 vs 175/198 for fp8 KV on the same checkpoint (statistically tied); NIAH 30/30 from 4k to 360k; needle retrieved at 460k depth; decode speed within noise of fp8 at matched context; zero OOMs. Signed-off-by: David Young <davidseanyoung@gmail.com> Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JzPRoS8j7b78iivwSmFv4y
…group scales Quantizes a random MLA latent through the op and dequantizes the cache record with a torch reference (E2M1 nibble table x per-group E4M3 scales): asserts the stored scales match E4M3(group_amax/6) within half a mantissa step, bounds the per-element NoPE error by the E2M1 grid half-gap (1.25x group scale), and checks the 16-byte pad is zeroed, the 16-bit RoPE lane is copied verbatim, and unmapped slots stay untouched. Skips cleanly without CUDA, on ROCm, and below SM100. Signed-off-by: David Young <davidseanyoung@gmail.com> Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JzPRoS8j7b78iivwSmFv4y
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📝 WalkthroughWalkthroughThis PR adds NVFP4 (Blackwell SM100/SM120) support for the DS-MLA concat-and-cache path, introducing a new CUDA kernel, host dispatcher, and stable ABI operator binding. It plumbs a new "nvfp4_ds_mla" kv-cache dtype through Python config, dtype utilities, MLA attention forward logic, the B12x sparse MLA backend, and KV cache page-size calculations, with an accompanying kernel test. ChangesNVFP4 DS-MLA Cache Support
Estimated code review effort: 4 (Complex) | ~60 minutes Sequence Diagram(s)sequenceDiagram
participant Caller
participant CustomOps as concat_and_cache_mla (Python)
participant Wrapper as concat_and_cache_nvfp4_mla (Python)
participant Op as torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla
participant Kernel as concat_and_cache_nvfp4_mla_kernel (CUDA)
Caller->>CustomOps: kv_c, k_pe, kv_cache, slot_mapping, kv_cache_dtype="nvfp4_ds_mla"
CustomOps->>Wrapper: delegate call
Wrapper->>Wrapper: _ensure_nvfp4_mla_cache_ext() if op missing
Wrapper->>Op: invoke stable ABI op
Op->>Kernel: launch with validated tensors
Kernel->>Kernel: pack NoPE FP4 values + scale bytes per group
Kernel->>Kernel: copy RoPE (k_pe) into tail bytes
Kernel-->>Op: kv_cache updated in place
Op-->>Caller: return
🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Actionable comments posted: 3
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@csrc/libtorch_stable/cache_kernels.cu`:
- Around line 1034-1056: The nvfp4 cache launch path in
concat_and_cache_nvfp4_mla is only compile-time gated today, so add a runtime
SM100+ device check before the kernel launch. In the ENABLE_NVFP4_SM100 /
ENABLE_NVFP4_SM120 block, validate the active device from
DeviceGuard/get_device_index and throw the explicit unsupported-device error for
older GPUs before reaching vllm::concat_and_cache_nvfp4_mla_kernel.
In `@tests/kernels/attention/test_cache.py`:
- Around line 903-911: Reset or reinitialize kv_cache after the opcheck call and
before calling ops.concat_and_cache_mla, so the public-wrapper validation starts
from a clean cache state. Use the existing test_cache setup around opcheck and
concat_and_cache_mla to locate the spot, and ensure the second call is verifying
routing/writes from scratch rather than reusing records written by
torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla.
In `@vllm/v1/attention/backends/mla/b12x_mla_sparse.py`:
- Around line 745-762: The prewarm KV cache layout in b12x_mla_sparse.py is now
dtype-dependent, but the _EXTEND_PREWARM_DONE de-duplication key in the prewarm
path does not include that layout choice. Update the key used around the prewarm
logic so it also distinguishes the cache layout/kv_cache_dtype in addition to
the existing device and shape fields, and keep the prewarm setup in the same
helper block that builds kv_cache and record_bytes. This ensures fp8_ds_mla and
nvfp4_ds_mla each run their own layout-specific prewarm instead of incorrectly
sharing one.
🪄 Autofix (Beta)
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
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Run ID: 088e5cf5-8e84-4b66-8ffb-8afc293a192e
📒 Files selected for processing (10)
csrc/libtorch_stable/cache_kernels.cucsrc/libtorch_stable/ops.hcsrc/libtorch_stable/torch_bindings.cpptests/kernels/attention/test_cache.pyvllm/_custom_ops.pyvllm/config/cache.pyvllm/model_executor/layers/attention/mla_attention.pyvllm/utils/torch_utils.pyvllm/v1/attention/backends/mla/b12x_mla_sparse.pyvllm/v1/kv_cache_interface.py
Comment on lines
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+1056
| #if defined(ENABLE_NVFP4_SM100) || defined(ENABLE_NVFP4_SM120) | ||
| int block_size = kv_cache.size(1); | ||
| int kv_c_stride = kv_c.stride(0); | ||
| int k_pe_stride = k_pe.stride(0); | ||
| int block_stride = kv_cache.stride(0); | ||
| int entry_stride = kv_cache.stride(1); | ||
|
|
||
| const torch::stable::accelerator::DeviceGuard device_guard( | ||
| kv_c.get_device_index()); | ||
| const cudaStream_t stream = get_current_cuda_stream(); | ||
|
|
||
| dim3 grid(num_tokens); | ||
| dim3 block(128); | ||
| VLLM_STABLE_DISPATCH_HALF_TYPES( | ||
| kv_c.scalar_type(), "concat_and_cache_nvfp4_mla", [&] { | ||
| vllm::concat_and_cache_nvfp4_mla_kernel<scalar_t> | ||
| <<<grid, block, 0, stream>>>( | ||
| reinterpret_cast<scalar_t*>(kv_c.data_ptr()), | ||
| reinterpret_cast<scalar_t*>(k_pe.data_ptr()), | ||
| reinterpret_cast<uint8_t*>(kv_cache.data_ptr()), | ||
| slot_mapping.const_data_ptr<int64_t>(), block_stride, | ||
| entry_stride, kv_c_stride, k_pe_stride, kv_lora_rank, pe_dim, | ||
| block_size); |
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🩺 Stability & Availability | 🟠 Major | ⚡ Quick win
🧩 Analysis chain
🏁 Script executed:
#!/bin/bash
set -euo pipefail
# Inspect the relevant region around the launch site.
sed -n '1000,1085p' csrc/libtorch_stable/cache_kernels.cu
# Search for nearby architecture/runtime guards in this file and related NVFP4 launch paths.
rg -n "SM100|sm100|Blackwell|cudaGetDeviceProperties|DeviceGuard|get_device_index|nvfp4|ENABLE_NVFP4" csrc/libtorch_stable/cache_kernels.cu
# Find all NVFP4 kernel launch sites in the repo to compare guard patterns.
rg -n "concat_and_cache_nvfp4|nvfp4" csrc -g'*.cu' -g'*.cc' -g'*.cpp' -g'*.h'Repository: local-inference-lab/vllm
Length of output: 15003
Add a runtime SM100+ guard before launching. ENABLE_NVFP4_SM100/ENABLE_NVFP4_SM120 only gates compilation; this call still needs a runtime SM100+ check so an older active device fails with the explicit error instead of hitting the kernel launch path.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@csrc/libtorch_stable/cache_kernels.cu` around lines 1034 - 1056, The nvfp4
cache launch path in concat_and_cache_nvfp4_mla is only compile-time gated
today, so add a runtime SM100+ device check before the kernel launch. In the
ENABLE_NVFP4_SM100 / ENABLE_NVFP4_SM120 block, validate the active device from
DeviceGuard/get_device_index and throw the explicit unsupported-device error for
older GPUs before reaching vllm::concat_and_cache_nvfp4_mla_kernel.
Comment on lines
+903
to
+911
| opcheck( | ||
| torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla, | ||
| (kv_c, k_pe, kv_cache, slot_mapping, scale), | ||
| test_utils=DEFAULT_OPCHECK_TEST_UTILS, | ||
| ) | ||
|
|
||
| # Route through the public entry point: concat_and_cache_mla dispatches | ||
| # to the nvfp4 op on kv_cache_dtype == "nvfp4_ds_mla". | ||
| ops.concat_and_cache_mla(kv_c, k_pe, kv_cache, slot_mapping, kv_cache_dtype, scale) |
There was a problem hiding this comment.
🎯 Functional Correctness | 🟡 Minor | ⚡ Quick win
Reset kv_cache after opcheck before validating the public route.
opcheck invokes the private op with the same kv_cache, so the later public-wrapper validation can pass from already-written records even if routing becomes a no-op or partial write.
Suggested fix
opcheck(
torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla,
(kv_c, k_pe, kv_cache, slot_mapping, scale),
test_utils=DEFAULT_OPCHECK_TEST_UTILS,
)
+ kv_cache.zero_()
# Route through the public entry point: concat_and_cache_mla dispatches📝 Committable suggestion
‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.
Suggested change
| opcheck( | |
| torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla, | |
| (kv_c, k_pe, kv_cache, slot_mapping, scale), | |
| test_utils=DEFAULT_OPCHECK_TEST_UTILS, | |
| ) | |
| # Route through the public entry point: concat_and_cache_mla dispatches | |
| # to the nvfp4 op on kv_cache_dtype == "nvfp4_ds_mla". | |
| ops.concat_and_cache_mla(kv_c, k_pe, kv_cache, slot_mapping, kv_cache_dtype, scale) | |
| opcheck( | |
| torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla, | |
| (kv_c, k_pe, kv_cache, slot_mapping, scale), | |
| test_utils=DEFAULT_OPCHECK_TEST_UTILS, | |
| ) | |
| kv_cache.zero_() | |
| # Route through the public entry point: concat_and_cache_mla dispatches | |
| # to the nvfp4 op on kv_cache_dtype == "nvfp4_ds_mla". | |
| ops.concat_and_cache_mla(kv_c, k_pe, kv_cache, slot_mapping, kv_cache_dtype, scale) |
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@tests/kernels/attention/test_cache.py` around lines 903 - 911, Reset or
reinitialize kv_cache after the opcheck call and before calling
ops.concat_and_cache_mla, so the public-wrapper validation starts from a clean
cache state. Use the existing test_cache setup around opcheck and
concat_and_cache_mla to locate the spot, and ensure the second call is verifying
routing/writes from scratch rather than reusing records written by
torch.ops._C_cache_ops.concat_and_cache_nvfp4_mla.
Comment on lines
+745
to
+762
| # GLM cache records are 656 B/token (fp8_ds_mla) or 432 B/token | ||
| # (nvfp4_ds_mla); the real KV cache is laid out | ||
| # (num_blocks, block_size, record_bytes) (see the allocator at the | ||
| # block-shape branch above), so a page's stride(0) = | ||
| # block_size*record_bytes. The prewarm dummy must match that layout -- | ||
| # (1, block_size, record_bytes) -- so _cache_block_stride_bytes sees | ||
| # stride >= page_size*record_bytes. The prior (block_size, 1, ...) | ||
| # shape put block_size in dim 0, giving stride(0) = record_bytes < | ||
| # page_size*record_bytes, which tripped the SM120 stride assertion | ||
| # whenever this prewarm ran (i.e. spec + cudagraphs, the first config | ||
| # to reach here; verifier-only and eager-snap both skipped it). | ||
| # One page is enough: prewarm top-k indices all point at slot zero. | ||
| # Record width follows the cache dtype. | ||
| record_bytes = 432 if self.kv_cache_dtype == "nvfp4_ds_mla" else 656 | ||
| kv_cache = torch.zeros( | ||
| (1, self.block_size, 656), dtype=torch.uint8, device=self.device | ||
| (1, self.block_size, record_bytes), | ||
| dtype=torch.uint8, | ||
| device=self.device, |
There was a problem hiding this comment.
🩺 Stability & Availability | 🟠 Major | ⚡ Quick win
Include the cache layout in the prewarm de-duplication key.
Line 758 makes the prewarm KV layout dtype-dependent, but _EXTEND_PREWARM_DONE is keyed only by device/dimensions above this block. In a process that initializes both fp8_ds_mla and nvfp4_ds_mla with matching dimensions, the second dtype can skip its layout-specific prewarm and defer compilation/stride validation into the first real call.
Proposed fix
def _prewarm_extend_kernels_once(self, max_batched: int) -> None:
if self.device.type != "cuda":
return
+ record_bytes = 432 if self.kv_cache_dtype == "nvfp4_ds_mla" else 656
key = (
self.device.index,
self.q_head_dim,
self.kv_lora_rank,
self._kernel_num_heads,
int(self.topk_tokens),
int(self.block_size),
+ record_bytes,
+ self._b12x_scale_format,
bool(self.need_to_return_lse_for_decode),
)
if key in _EXTEND_PREWARM_DONE:
return
_EXTEND_PREWARM_DONE.add(key)
@@
- record_bytes = 432 if self.kv_cache_dtype == "nvfp4_ds_mla" else 656
kv_cache = torch.zeros(
(1, self.block_size, record_bytes),
dtype=torch.uint8,
device=self.device,📝 Committable suggestion
‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.
Suggested change
| # GLM cache records are 656 B/token (fp8_ds_mla) or 432 B/token | |
| # (nvfp4_ds_mla); the real KV cache is laid out | |
| # (num_blocks, block_size, record_bytes) (see the allocator at the | |
| # block-shape branch above), so a page's stride(0) = | |
| # block_size*record_bytes. The prewarm dummy must match that layout -- | |
| # (1, block_size, record_bytes) -- so _cache_block_stride_bytes sees | |
| # stride >= page_size*record_bytes. The prior (block_size, 1, ...) | |
| # shape put block_size in dim 0, giving stride(0) = record_bytes < | |
| # page_size*record_bytes, which tripped the SM120 stride assertion | |
| # whenever this prewarm ran (i.e. spec + cudagraphs, the first config | |
| # to reach here; verifier-only and eager-snap both skipped it). | |
| # One page is enough: prewarm top-k indices all point at slot zero. | |
| # Record width follows the cache dtype. | |
| record_bytes = 432 if self.kv_cache_dtype == "nvfp4_ds_mla" else 656 | |
| kv_cache = torch.zeros( | |
| (1, self.block_size, 656), dtype=torch.uint8, device=self.device | |
| (1, self.block_size, record_bytes), | |
| dtype=torch.uint8, | |
| device=self.device, | |
| if self.device.type != "cuda": | |
| return | |
| record_bytes = 432 if self.kv_cache_dtype == "nvfp4_ds_mla" else 656 | |
| key = ( | |
| self.device.index, | |
| self.q_head_dim, | |
| self.kv_lora_rank, | |
| self._kernel_num_heads, | |
| int(self.topk_tokens), | |
| int(self.block_size), | |
| record_bytes, | |
| self._b12x_scale_format, | |
| bool(self.need_to_return_lse_for_decode), | |
| ) | |
| if key in _EXTEND_PREWARM_DONE: | |
| return | |
| _EXTEND_PREWARM_DONE.add(key) | |
| # GLM cache records are 656 B/token (fp8_ds_mla) or 432 B/token | |
| # (nvfp4_ds_mla); the real KV cache is laid out | |
| # (num_blocks, block_size, record_bytes) (see the allocator at the | |
| # block-shape branch above), so a page's stride(0) = | |
| # block_size*record_bytes. The prewarm dummy must match that layout -- | |
| # (1, block_size, record_bytes) -- so _cache_block_stride_bytes sees | |
| # stride >= page_size*record_bytes. The prior (block_size, 1, ...) | |
| # shape put block_size in dim 0, giving stride(0) = record_bytes < | |
| # page_size*record_bytes, which tripped the SM120 stride assertion | |
| # whenever this prewarm ran (i.e. spec + cudagraphs, the first config | |
| # to reach here; verifier-only and eager-snap both skipped it). | |
| # One page is enough: prewarm top-k indices all point at slot zero. | |
| # Record width follows the cache dtype. | |
| kv_cache = torch.zeros( | |
| (1, self.block_size, record_bytes), | |
| dtype=torch.uint8, | |
| device=self.device, |
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@vllm/v1/attention/backends/mla/b12x_mla_sparse.py` around lines 745 - 762,
The prewarm KV cache layout in b12x_mla_sparse.py is now dtype-dependent, but
the _EXTEND_PREWARM_DONE de-duplication key in the prewarm path does not include
that layout choice. Update the key used around the prewarm logic so it also
distinguishes the cache layout/kv_cache_dtype in addition to the existing device
and shape fields, and keep the prewarm setup in the same helper block that
builds kv_cache and record_bytes. This ensures fp8_ds_mla and nvfp4_ds_mla each
run their own layout-specific prewarm instead of incorrectly sharing one.
lukealonso
merged commit Jul 14, 2026
9fd2b9b
into
local-inference-lab:dev/eldritch-enlightenment
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Problem
fp8_ds_mlastores the sparse-MLA KV record at 656 B/token/layer (512 B fp8NoPE + 16 B fp32 tile scales + 128 B BF16 RoPE). For GLM-5.2-class models on
4× 96 GB that caps the KV pool at ~307k tokens (
--gpu-memory-utilization 0.96) — barely one 240krequest resident, and
--max-model-lenis stuck at ~240k. The 512-dim MLAlatent is the dominant KV cost, and it tolerates 4-bit storage with per-group
scales: NVFP4 (E2M1 data + per-16-element E4M3 scales) cuts the record to
432 B/token/layer (256 B FP4 NoPE + 32 B E4M3 group scales + 16 B
alignment pad + 128 B BF16 RoPE) — measured 37,032 vs 54,728 B/token all
layers (−32%), i.e. +39–48% pool at equal budget.
Fix
A new opt-in KV cache dtype,
--kv-cache-dtype nvfp4_ds_mla, for theB12X_MLA_SPARSEbackend. Behavior is unchanged unless opted in: everychange is gated on
kv_cache_dtype == "nvfp4_ds_mla", and fp8_ds_mla servingtakes byte-identical code paths — including the b12x call signatures.
Write side:
concat_and_cache_nvfp4_mlaincsrc/libtorch_stable/cache_kernels.cu(+
ops.hdecl,_C_cache_opsschema/impl): quantizes the 512-dim latentto packed E2M1 with per-16-group E4M3 scales (implicit global scale 1.0 —
the
scaleargument keeps theconcat_and_cache_mlasignature family butis unused), zero-fills the 16-byte pad, copies the RoPE lane verbatim in
16-bit. Guarded by
ENABLE_NVFP4_SM100/SM120; a build without those raisesa clear "requires SM100+ (Blackwell)" error at first use.
concat_and_cache_mla(both the C++ host and the Python wrapper) dispatchesto it on the new dtype, so all existing call sites work unchanged.
_custom_opscan alternatively lazy-load a companionvllm/_nvfp4_mla_cache_C.soiff the main build lacks the op — lets thefeature ship as an overlay on an existing image without rebuilding the main
extension (that is how the validation image below ran it).
Read side (companion b12x PR, see below):
B12xMLASparseImplpassesscale_format=2(b12xScaleFormat.NVFP4_E4M3) into the shared_make_plan(covers both_decode_planand_extend_plan), all sixdecode/extend forward call sites, and the prewarm forwards; the scratch caps
additionally carry
kv_cache_dtypeso the planner sizes for the 432 Brecord. These kwargs are forwarded only when serving
nvfp4_ds_mla, sofp8 serving keeps the stock b12x call signature and runs on a b12x tree
without the nvfp4 read-path port. Until that port is installed, requesting
nvfp4_ds_mlafails loudly at plan construction (unexpected-kwarg) — whichis correct, since the read path would not exist either.
Plumbing:
nvfp4_ds_mlaadded toCacheDType,STR_DTYPE_TO_TORCH_DTYPE(uint8),
is_quantized_kv_cache,KVQuantMode.NVFP4mapping, theMLAAttentionSpec/SlidingWindowMLASpecreal_page_size_bytes(432 ×block_size), the backend's
supported_kv_cache_dtypes+get_kv_cache_shape((num_blocks, block_size, 432)), and the sparse-MLAdtype canonicalization (B12X accepts it;
FLASHMLA_SPARSEstillcanonicalizes to
fp8_ds_mla).CUDA-graph safety: the cache dtype is fixed at engine boot, so the record
width and the b12x kwargs are process-lifetime constants — every captured
graph bakes in exactly one record format and there is no per-step branching.
The spec+cudagraph prewarm dummy allocates
(1, block_size, record_bytes)so the SM120 block-stride assertion sees the same layout as the real
allocator for either record width.
Results
Checkpoint:
madeby561/GLM-5.2-MXFP8-NVFP4-NF3-Hybrid(GLM-5.2 753B, all 256 experts), 4× RTX PRO 6000 Blackwell (SM120), TP4 +
DCP4, MTP-5,
B12X_MLA_SPARSE+--moe-backend b12x. Same weights, sameimage, same machine — the A/B isolates one variable: how the MLA KV is stored.
Capacity:
--gpu-memory-utilization 0.96,--max-num-batched-tokens 4096)0.968/2048)--max-model-lenQuality (same checkpoint both sides):
Net across the 258 scored hard questions: nvfp4 176 correct vs fp8 175.
Speed: decode is expert-bandwidth-bound, so the KV dtype is speed-neutral at
matched context (real-content median ≈71 t/s on both sides; fixed-harness
126.2 / 123.5 / 113.8 / 118.9 t/s at 1k / 32k / 128k / 200k) — and the 4-bit
side keeps decoding at 69.7 t/s with 460k tokens resident, a context the
fp8 pool cannot hold at all. Prefill unchanged (~1.6–3.5k tok/s band).
Limitations
kv_lora_rank == 512,pe_dim == 64, 16-bit input(GLM/DSA sparse-MLA family) — checked with clear errors.
the op registered but raise a descriptive error if it is ever called.
B12X_MLA_SPARSEonly;FLASHMLA_SPARSEcontinues to canonicalize tofp8_ds_mla.nvfp4_ds_mlaneeds the b12x read-path companion (next section);fp8 serving needs nothing new.
Companion PR (b12x read path)
The decode/extend read path lives in b12x: a
ScaleFormat.NVFP4_E4M3(== 2)branch in the unified SM120 sparse-MLA decode/extend kernels, plus
B12XSparseMLAScratchCapsacceptingkv_cache_dtype: strandscale_format: int | None. Our port of that path is what served everynumber above; it currently targets the b12x tree the validation image was
built from, and we are re-porting it onto current b12x (
e44cb77) — thecompanion PR follows when that lands. Merge order is safe in either
direction: this PR alone changes nothing for fp8 users and fails loudly for
nvfp4 until the b12x side is present.
Tests
tests/kernels/attention/test_cache.py::test_concat_and_cache_nvfp4_mla,mirroring
test_concat_and_cache_ds_mla: quantizes a random latent throughthe op (opcheck included, routed via the public
concat_and_cache_mladispatch) and dequantizes the cache record with a torch reference (E2M1
nibble table × per-group E4M3 scales). Asserts the stored scales match
E4M3(group_amax / 6)within half a mantissa step, bounds the per-elementNoPE error by the E2M1 grid half-gap (1.25× group scale), and checks the
16-byte pad is zeroed, the RoPE lane is a verbatim 16-bit copy, and unmapped
slots stay untouched. Skips cleanly without CUDA, on ROCm, and below SM100,
so GPU-less CI is unaffected.
Testing status of this exact branch: the prep machine has no CUDA 13.2
toolchain, so no full build was run here —
python -m py_compilepasses onevery touched Python file, and the csrc kernel + host function are
byte-identical to the extension source whose compiled binary served the full
validation campaign above (same code, re-hosted in-tree). The in-tree
placement itself still wants one CI/image build for compile confirmation;
happy to iterate if your build turns anything up.
🤖 Generated with Claude Code
https://claude.ai/code/session_01JzPRoS8j7b78iivwSmFv4y
Summary by CodeRabbit
New Features
nvfp4_ds_mlaKV cache format in MLA attention and cache operations.Bug Fixes
Tests