fix(mp): preserve async store events and opaque page tails

[yatesdr]

Purpose

Prevent three independent sources of silent cache corruption in the asynchronous
LMCache MP path used by r12:

1. a store losing its producer IPC event while the sidecar can still be waiting
   on that event and reading the associated GPU pages; and
2. a padded attention transfer omitting model-owned opaque state appended after
   the semantic KV payload; and
3. byte-odd opaque rows (notably the 561-byte FP8 MLA record) being rejected by
   a vectorized CUDA copy path that requires two-byte alignment.

A long request can submit multiple incremental stores under one request ID.
The adapter's request-keyed event entry is then overwritten by the next store.
Without an independent reference owned by each remote-store future, an earlier
event may be destroyed before the sidecar completes its wait and device read,
allowing incomplete or reused page contents to be committed to persistent L2.

GLM-5.3 C4 also appends an FP8 index-cache tail to every MLA page. vLLM includes
that tail in spec.page_size_bytes, but the padded-page adapter previously
derived its transfer width only from tensor.shape[1:]. A cache hit therefore
restored CKV without the C4 selector state. This was especially visible on
TP4/DCP4 without full-CKV gather: lookup and transfer counters reported a full
hit, but deterministic needle prompts returned garbled or degenerate answers.

Change

• Retain every producer event on its corresponding device-aware store future.
• Keep the future in the existing in-flight set until remote completion.
• Extend the regression to issue two stores for one request and verify that
  both distinct events remain attached to their own futures and both stores
  are drained.
• Build padded attention views from the complete declared page size, not only
  the semantic tensor shape.
• Validate that the declared page fits its physical block stride, while
  preserving every declared opaque byte in the transfer view.
• Use the vectorized CUDA copy path when its alignment contract holds and an
  exact byte-copy CUDA fallback for odd row widths.
• Add a regression proving an opaque page tail is included in the zero-copy
  transfer view, plus a compiled D2H/H2D round-trip for padded 561-byte rows.

This does not change DCP geometry, cache keys, block IDs, object grouping, or the
cuMem lifecycle introduced by the base stack. Existing attention pages without
an opaque tail retain their prior shape and transfer width.

Stack and r12 integration

This is a stacked PR based directly on #34 head
801b6ce335a46628bd87b70b8c1c263f45a380f3, which is the LMCache source pin
in voipmonitor/vllm:jovian-judgement-community-20260901-r12.

It must be composed on top of #33/#34; installing the separate
b5308054 integration wheel wholesale would discard the r12-only work. The
equivalent correction is already present on
integration/glm53-upstream-consolidation at c4e6ec5e.

Validation

Against the exact immutable r12 image
sha256:80dc3c3481255c123b3fe9ff164a879b7a141292389d29b0fd04a8472e6bf15d
with the proposed Python files overlaid:

• Compiled CUDA D2H/H2D transfer of padded 561-byte rows passed exactly,
  including verification that dim-0 padding remains untouched.
• 2 passed: LMCache-driven preemption/store-event lifetime tests.
• 74 passed: complete DCP geometry, rank ownership, namespace, and padded-page
  integration test file, including the new opaque-tail regression.
• 163 passed: focused recurrent and multiprocess transfer suites.
• git diff --check passed.

Runtime reproductions that motivated the page-tail fix:

• a 110,592-token persistent-L2 hit restored all expected keys on all four
  ranks but entered degenerate reasoning, while a never-cached salt answered
  every deterministic needle correctly; and
• a shorter immediate L1-only hit returned garbled codewords after only vLLM
  APC was cleared, excluding filesystem, S3, restart, and hash nondeterminism.

Fresh-store exact-content acceptance passed on the r12 runtime for TP4/DCP4 and
TP4/DCP1 with FP8 MLA KV: APC-only reset/L1 restores and full process
restart/L2 restores returned the exact deterministic codeword, with LMCache
logs attributing the restored keys to the expected tier. Objects created by the
defective transfer width were not reused for those gates.

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[yatesdr]

Final r15 integration update

This PR now includes the two page-geometry fixes discovered during the r15
qualification pass:

• 64f2abcb: transfer packed GLM-5.3-Flash NVFP4 attention pages as opaque
  physical slots while preserving their logical token geometry.
• 2579f617: transfer the exact-fit GLM-5.3-Flash DCP1 recurrent page
  (4096 * 265 = 1,085,440 bytes) as one opaque physical slot. DCP2/4/8 retain
  the existing tiled layouts.

The equivalent tested integration head is 0b8eedb6c9c268c62234eff54229f239123678f0.
The r15 candidate passed exact cold/APC/L1/restart-L2 content checks on TP4 for
DCP1, DCP2, and DCP4 with both fp8_ds_mla and nvfp4_ds_mla. DCP4 NVFP4 also
passed five repeated APC-reset/L1 restores. TP8 is source-audited but was not
executed because an eight-GPU host was unavailable.

The allocator behavior is intentionally unchanged from upstream LMCache. The
private on-demand allocator experiments are not included.

[voipmonitor]

Integration evidence and merge scope

Status: the #35 cache-transfer behavior is qualified in the R20 consolidated
LMCache tree; this stacked PR is not a direct-to-dev merge artifact.

The focused implementation evidence passed compiled D2H/H2D transfer of
byte-odd 561-byte rows, two asynchronous store-event lifetime cases, 74 DCP
geometry/page-transfer cases, and 163 recurrent and multiprocess transfer
cases. The opaque page-tail test verifies that bytes declared by the cache page
specification are transferred even when they are not represented by the
semantic tensor shape.

The consolidated tree installed in
voipmonitor/vllm:jovian-judgement-community-20260903-r20 passed FP8 and
NVFP4 cold compute, vLLM prefix reuse, LMCache DRAM restore, and filesystem
restore after restarting vLLM and the LMCache sidecar. External cache data was
compared byte-for-byte on every TP rank across target attention, recurrent
state, and DFlash sliding attention. DFlash2 restored 12,288 prompt tokens from
filesystem L2 after restart.

#35 depends on its declared integration base. Port the functional commits in
order and preserve their authors; merging the PR head directly into LMCache
dev does not reproduce the qualified source tree.

[lukealonso]

Landed on canonical dev in 5031e29 after the full LMCache suite (4,841 passed, 167 skipped, 1 xpassed), focused native CUDA transfer tests, canonical-vLLM integration coverage, and all pre-commit hooks passed. Closing the source PR because its base was the prerequisite integration branch rather than dev.