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21 changes: 21 additions & 0 deletions llvm/lib/Target/X86/X86PfmCounters.td
Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,27 @@ def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;

def AlderLakePfmCounters : ProcPfmCounters {
let CycleCounter = UnhaltedCoreCyclesPfmCounter;
let UopsCounter = UopsIssuedPfmCounter;
let IssueCounters = [
PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">,
PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">,
PfmIssueCounter<"ADLPPort02", "uops_dispatched_port:port_2_3_10">,
PfmIssueCounter<"ADLPPort03", "uops_dispatched_port:port_2_3_10">,
PfmIssueCounter<"ADLPPort04", "uops_dispatched_port:port_4_9">,
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Use ADLPPort04_09 instead - adding the other ProcResGroup combos to X86SchedAlderlakeP.td shouldn't be a problem.

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Can't believe I missed that one along with 1-2 others. I've added in the ones that were missing as well to X86SchedAlderlakeP.td, along with a ADLPPortAny ProcResGroup so that all of the overlapping groups have a super group (I believe that won't cause any issues?).

PfmIssueCounter<"ADLPPort05", "uops_dispatched_port:port_5_11">,
PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">,
PfmIssueCounter<"ADLPPort07", "uops_dispatched_port:port_7_8">,
PfmIssueCounter<"ADLPPort08", "uops_dispatched_port:port_7_8">,
PfmIssueCounter<"ADLPPort09", "uops_dispatched_port:port_4_9">,
PfmIssueCounter<"ADLPPort10", "uops_dispatched_port:port_2_3_10">,
PfmIssueCounter<"ADLPPort11", "uops_dispatched_port:port_5_11">,
];
let ValidationCounters = DefaultIntelPfmValidationCounters;
}
def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;

// AMD X86 Counters.
defvar DefaultAMDPfmValidationCounters = [
PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
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