[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

XinWang10 · 2023-12-15T10:05:23Z

R16-R31 was added into GPRs in #70958,
This patch supports the encoding/decoding for promoted SHA instruction in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

llvmbot · 2023-12-15T10:05:51Z

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-x86

Author: None (XinWang10)

Changes

R16-R31 was added into GPRs in #70958,
This patch supports the encoding/decoding for promoted SHA instruction in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

Patch is 21.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/75582.diff

23 Files Affected:

(modified) llvm/lib/Target/X86/X86InstrSSE.td (+71-24)
(added) llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt (+10)
(added) llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt (+10)
(added) llvm/test/MC/X86/apx/sha1msg1-att.s (+9)
(added) llvm/test/MC/X86/apx/sha1msg1-intel.s (+10)
(added) llvm/test/MC/X86/apx/sha1msg2-att.s (+9)
(added) llvm/test/MC/X86/apx/sha1msg2-intel.s (+9)
(added) llvm/test/MC/X86/apx/sha1nexte-att.s (+9)
(added) llvm/test/MC/X86/apx/sha1nexte-intel.s (+9)
(added) llvm/test/MC/X86/apx/sha1rnds4-att.s (+9)
(added) llvm/test/MC/X86/apx/sha1rnds4-intel.s (+9)
(added) llvm/test/MC/X86/apx/sha256msg1-att.s (+9)
(added) llvm/test/MC/X86/apx/sha256msg1-intel.s (+9)
(added) llvm/test/MC/X86/apx/sha256msg2-att.s (+9)
(added) llvm/test/MC/X86/apx/sha256msg2-intel.s (+9)
(added) llvm/test/MC/X86/apx/sha256rnds2-att.s (+9)
(added) llvm/test/MC/X86/apx/sha256rnds2-intel.s (+10)
(modified) llvm/test/TableGen/x86-fold-tables.inc (+7)

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index cf57fe562ed5c4..acf068d38b5de9 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in {
 
 // FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
-                      X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
-  def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
-             (ins VR128:$src1, VR128:$src2),
-             !if(UsesXMM0,
-                 !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
-                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
-             [!if(UsesXMM0,
-                  (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
-                  (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
-             T8PS, Sched<[sched]>;
-
-  def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
-             (ins VR128:$src1, i128mem:$src2),
-             !if(UsesXMM0,
-                 !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
-                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
-             [!if(UsesXMM0,
-                  (set VR128:$dst, (IntId VR128:$src1,
-                    (memop addr:$src2), XMM0)),
-                  (set VR128:$dst, (IntId VR128:$src1,
-                    (memop addr:$src2))))]>, T8PS,
-             Sched<[sched.Folded, sched.ReadAfterFold]>;
+                      X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
+  def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
+                    (ins VR128:$src1, VR128:$src2),
+                    !if(UsesXMM0,
+                        !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+                        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+                    [!if(UsesXMM0,
+                         (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
+                         (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
+                    T8PS, Sched<[sched]>;
+
+  def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
+                    (ins VR128:$src1, i128mem:$src2),
+                    !if(UsesXMM0,
+                        !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+                        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+                    [!if(UsesXMM0,
+                         (set VR128:$dst, (IntId VR128:$src1,
+                           (memop addr:$src2), XMM0)),
+                         (set VR128:$dst, (IntId VR128:$src1,
+                           (memop addr:$src2))))]>, T8PS,
+                    Sched<[sched.Folded, sched.ReadAfterFold]>;
 }
 
-let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
+let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
   def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
                          (ins VR128:$src1, VR128:$src2, u8imm:$src3),
                          "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6757,7 +6757,7 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
 
   let Uses=[XMM0] in
   defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
-                                SchedWriteVecIMul.XMM, 1>;
+                                SchedWriteVecIMul.XMM, "", 1>;
 
   defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
                                SchedWriteVecIMul.XMM>;
@@ -6765,12 +6765,59 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
                                SchedWriteVecIMul.XMM>;
 }
 
+let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode]in {
+  def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
+                             (ins VR128:$src1, VR128:$src2, u8imm:$src3),
+                             "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+                             [(set VR128:$dst,
+                               (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
+                                (i8 timm:$src3)))]>,
+                         EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>;
+  def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
+                             (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
+                             "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+                             [(set VR128:$dst,
+                               (int_x86_sha1rnds4 VR128:$src1,
+                                (memop addr:$src2),
+                                (i8 timm:$src3)))]>,
+                         EVEX_NoCD8, T_MAP4PS,
+                         Sched<[SchedWriteVecIMul.XMM.Folded,
+                                SchedWriteVecIMul.XMM.ReadAfterFold]>;
+
+  defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
+                                   SchedWriteVecIMul.XMM, "_EVEX">,
+                        EVEX_NoCD8, T_MAP4PS;
+  defm SHA1MSG1  : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
+                              SchedWriteVecIMul.XMM, "_EVEX">,
+                   EVEX_NoCD8, T_MAP4PS;
+  defm SHA1MSG2  : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
+                              SchedWriteVecIMul.XMM, "_EVEX">,
+                   EVEX_NoCD8, T_MAP4PS;
+
+  let Uses=[XMM0] in
+  defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
+                                SchedWriteVecIMul.XMM, "_EVEX", 1>,
+                     EVEX_NoCD8, T_MAP4PS;
+
+  defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
+                               SchedWriteVecIMul.XMM, "_EVEX">,
+                    EVEX_NoCD8, T_MAP4PS;
+  defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
+                               SchedWriteVecIMul.XMM, "_EVEX">,
+                    EVEX_NoCD8, T_MAP4PS;
+}
+
 // Aliases with explicit %xmm0
 def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
                 (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
 def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
                 (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
 
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+                (SHA256RNDS2rr_EVEX VR128:$dst, VR128:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+                (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;
+
 //===----------------------------------------------------------------------===//
 // AES-NI Instructions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
new file mode 100644
index 00000000000000..1c94fa88a3d3cf
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha1msg1	%xmm13, %xmm12
+# INTEL: sha1msg1	xmm12, xmm13
+0x45,0x0f,0x38,0xc9,0xe5
+
+# ATT:   sha1msg1	291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
new file mode 100644
index 00000000000000..5fd17d9f326006
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha1msg2	%xmm13, %xmm12
+# INTEL: sha1msg2	xmm12, xmm13
+0x45,0x0f,0x38,0xca,0xe5
+
+# ATT:   sha1msg2	291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
new file mode 100644
index 00000000000000..3c5eae3d7177fc
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha1nexte	%xmm13, %xmm12
+# INTEL: sha1nexte	xmm12, xmm13
+0x45,0x0f,0x38,0xc8,0xe5
+
+# ATT:   sha1nexte	291(%r28,%r29,4), %xmm12
+# INTEL: sha1nexte	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
new file mode 100644
index 00000000000000..a05f17739606ac
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha1rnds4	$123, %xmm13, %xmm12
+# INTEL: sha1rnds4	xmm12, xmm13, 123
+0x45,0x0f,0x3a,0xcc,0xe5,0x7b
+
+# ATT:   sha1rnds4	$123, 291(%r28,%r29,4), %xmm12
+# INTEL: sha1rnds4	xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
+0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
new file mode 100644
index 00000000000000..b4c14866647dd6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha256msg1	%xmm13, %xmm12
+# INTEL: sha256msg1	xmm12, xmm13
+0x45,0x0f,0x38,0xcc,0xe5
+
+# ATT:   sha256msg1	291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
new file mode 100644
index 00000000000000..75099b428e2b67
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha256msg2	%xmm13, %xmm12
+# INTEL: sha256msg2	xmm12, xmm13
+0x45,0x0f,0x38,0xcd,0xe5
+
+# ATT:   sha256msg2	291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
new file mode 100644
index 00000000000000..1ca60aa9e9b1a2
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sha256rnds2	%xmm0, %xmm13, %xmm12
+# INTEL: sha256rnds2	xmm12, xmm13, xmm0
+0x45,0x0f,0x38,0xcb,0xe5
+
+# ATT:   sha256rnds2	%xmm0, 291(%r28,%r29,4), %xmm12
+# INTEL: sha256rnds2	xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
+0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/sha1msg1-att.s b/llvm/test/MC/X86/apx/sha1msg1-att.s
new file mode 100644
index 00000000000000..900b1b703c48ba
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg1-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg1	%xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
+         sha1msg1	%xmm13, %xmm12
+
+# CHECK: sha1msg1	291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1msg1	291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1msg1-intel.s b/llvm/test/MC/X86/apx/sha1msg1-intel.s
new file mode 100644
index 00000000000000..bd574633445241
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg1-intel.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg1	xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
+         sha1msg1	xmm12, xmm13
+
+# CHECK: sha1msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+         
\ No newline at end of file
diff --git a/llvm/test/MC/X86/apx/sha1msg2-att.s b/llvm/test/MC/X86/apx/sha1msg2-att.s
new file mode 100644
index 00000000000000..62557e46f8b9d0
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg2	%xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
+         sha1msg2	%xmm13, %xmm12
+
+# CHECK: sha1msg2	291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1msg2	291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1msg2-intel.s b/llvm/test/MC/X86/apx/sha1msg2-intel.s
new file mode 100644
index 00000000000000..546a56263bbe20
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg2-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg2	xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
+         sha1msg2	xmm12, xmm13
+
+# CHECK: sha1msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha1nexte-att.s b/llvm/test/MC/X86/apx/sha1nexte-att.s
new file mode 100644
index 00000000000000..70e8300cb70a7c
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1nexte-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1nexte	%xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
+         sha1nexte	%xmm13, %xmm12
+
+# CHECK: sha1nexte	291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1nexte	291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1nexte-intel.s b/llvm/test/MC/X86/apx/sha1nexte-intel.s
new file mode 100644
index 00000000000000..1c890c3cda44ad
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1nexte-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1nexte	xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
+         sha1nexte	xmm12, xmm13
+
+# CHECK: sha1nexte	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha1nexte	xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha1rnds4-att.s b/llvm/test/MC/X86/apx/sha1rnds4-att.s
new file mode 100644
index 00000000000000..1d24c83a0b30e5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1rnds4-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1rnds4	$123, %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
+         sha1rnds4	$123, %xmm13, %xmm12
+
+# CHECK: sha1rnds4	$123, 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
+         sha1rnds4	$123, 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1rnds4-intel.s b/llvm/test/MC/X86/apx/sha1rnds4-intel.s
new file mode 100644
index 00000000000000..53620856bbf0fc
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1rnds4-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1rnds4	xmm12, xmm13, 123
+# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
+         sha1rnds4	xmm12, xmm13, 123
+
+# CHECK: sha1rnds4	xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
+         sha1rnds4	xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
diff --git a/llvm/test/MC/X86/apx/sha256msg1-att.s b/llvm/test/MC/X86/apx/sha256msg1-att.s
new file mode 100644
index 00000000000000..c6d833dc78039a
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg1-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg1	%xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
+         sha256msg1	%xmm13, %xmm12
+
+# CHECK: sha256msg1	291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha256msg1	291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha256msg1-intel.s b/llvm/test/MC/X86/apx/sha256msg1-intel.s
new file mode 100644
index 00000000000000..e3e96f9e2f7d55
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg1-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg1	xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
+         sha256msg1	xmm12, xmm13
+
+# CHECK: sha256msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha256msg1	xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha256msg2-att.s b/llvm/test/MC/X86/apx/sha256msg2-att.s
new file mode 100644
index 00000000000000..979ee88633b675
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg2	%xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
+         sha256msg2	%xmm13, %xmm12
+
+# CHECK: sha256msg2	291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha256msg2	291(%r28,%r29,4), %xmm12
\ No newline at end of file
diff --git a/llvm/test/MC/X86/apx/sha256msg2-intel.s b/llvm/test/MC/X86/apx/sha256msg2-intel.s
new file mode 100644
index 00000000000000..043633de1c0413
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg2-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg2	xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
+         sha256msg2	xmm12, xmm13
+
+# CHECK: sha256msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha256msg2	xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha256rnds2-att.s b/llvm/test/MC/X86/apx/sha256rnds2-att.s
new file mode 100644
index 00000000000000..56ae30a2e3a9e9
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256rnds2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256rnds2	%xmm0, %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
+         sha256rnds2	%xmm0, %xmm13, %xmm12
+
+# CHECK: sha256rnds2	%xmm0, 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
+         sha256rnds2	%xmm0, 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha256rnds2-intel.s b/llvm/test/MC/X86/apx/sha256rnds2-intel.s
new file mode 100644
index 00000000000000..4ae727de80b919
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256rnds2-intel.s
@@ -0,0 +1,10 @@
+
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256rnds2	xmm12, xmm13, xmm0
+# CHECK: encodin...
[truncated]

llvm/lib/Target/X86/X86InstrSSE.td

llvm/test/MC/X86/apx/sha256rnds2-att.s

llvm/lib/Target/X86/X86InstrSSE.td

llvm/test/MC/X86/apx/sha256rnds2-intel.s

llvm/test/TableGen/x86-fold-tables.inc

github-actions · 2023-12-18T07:11:33Z

✅ With the latest revision this PR passed the C/C++ code formatter.

KanRobert · 2023-12-18T08:12:44Z

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

@@ -33,7 +33,9 @@ struct ManualMapEntry {

 // List of instructions requiring explicitly aligned memory.
 const char *ExplicitAlign[] = {"MOVDQA",  "MOVAPS",  "MOVAPD",  "MOVNTPS",
-                               "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
+                               "MOVNTPD", "MOVNTDQ", "MOVNTDQA", "SHA1MSG1",
+                               "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4",


Format this.

Not addressed.

llvm/lib/Target/X86/X86InstrSSE.td

phoebewang

LGTM.

phoebewang · 2023-12-18T08:26:11Z

llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt

@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT


Should be better to use file/cpuid instead of file/instruction to organize the test?

I have a justification...

We used to organize the test by cpuid. But the folder name apx here is the already about cpuid, and we have so many instructions for apx, if we put it into a test file, it would be very huge.

KanRobert

LGTM with one comment

…on (llvm#75582)" This reverts commit 037c220.

[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction

452f812

XinWang10 requested review from RKSimon, phoebewang and KanRobert December 15, 2023 10:05

llvmbot added backend:X86 mc Machine (object) code labels Dec 15, 2023

phoebewang reviewed Dec 15, 2023

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XinWang10 added 2 commits December 17, 2023 23:08

resolve comments

6fb9e33

Add 1 blank line end of file

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KanRobert reviewed Dec 18, 2023

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phoebewang approved these changes Dec 18, 2023

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resolve comment and fix 1 test

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KanRobert approved these changes Dec 19, 2023

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clang format

c0bb6be

XinWang10 merged commit 037c220 into llvm:main Dec 20, 2023
4 checks passed

FreddyLeaf mentioned this pull request Apr 18, 2024

[X86][APX] Remove KEYLOCKER and SHA promotions from EVEX MAP4. #89173

Merged

FreddyLeaf added a commit to FreddyLeaf/llvm-project that referenced this pull request Apr 18, 2024

Revert "[X86][MC] Support Enc/Dec for EGPR for promoted SHA instructi…

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…on (llvm#75582)" This reverts commit 037c220.

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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

XinWang10 commented Dec 15, 2023

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		@@ -0,0 +1,10 @@
		# RUN: llvm-mc --disassemble %s -triple=x86_64 \| FileCheck %s --check-prefixes=ATT

[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

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