[X86] Hygon Processors Initial enablement - #187622
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This patch adds initial support for several Hygon architectures. The Hygon architectures include: c86-4g-m4 c86-4g-m6 c86-4g-m7 This patch includes: Added Hygon architectures CPU targets recognition in Clang and LLVM Added Hygon architectures to target parser and host CPU detection Updated compiler-rt CPU model detection for Hygon architectures Added Hygon architectures to various optimizer tests
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@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang-driver Author: Xiaomeng Zhang (zhangxiaomeng-hygon) ChangesThis patch adds initial support for several Hygon architectures. The Hygon architectures include:
This patch includes:
Patch is 42.01 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/187622.diff 22 Files Affected:
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index cb941c94c84a7..fd30c7f8d61b9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -729,6 +729,15 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
+ case CK_C86_4G_M4:
+ defineCPUMacros(Builder, "c86-4g-m4");
+ break;
+ case CK_C86_4G_M6:
+ defineCPUMacros(Builder, "c86-4g-m6");
+ break;
+ case CK_C86_4G_M7:
+ defineCPUMacros(Builder, "c86-4g-m7");
+ break;
}
// Target properties.
@@ -1657,6 +1666,10 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER4:
case CK_ZNVER5:
case CK_ZNVER6:
+ // Hygon
+ case CK_C86_4G_M4:
+ case CK_C86_4G_M6:
+ case CK_C86_4G_M7:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c
index a65a07d81b8c0..bb4c65991ab50 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -211,4 +211,7 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver5");
(void)__builtin_cpu_is("znver6");
(void)__builtin_cpu_is("diamondrapids");
+ (void)__builtin_cpu_is("c86-4g-m4");
+ (void)__builtin_cpu_is("c86-4g-m6");
+ (void)__builtin_cpu_is("c86-4g-m7");
}
diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c
index 6a3ef5be67d8a..b05e025fca81c 100644
--- a/clang/test/Driver/x86-march.c
+++ b/clang/test/Driver/x86-march.c
@@ -263,6 +263,18 @@
// RUN: | FileCheck %s -check-prefix=znver6
// znver6: "-target-cpu" "znver6"
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m4 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m4
+// c86-4g-m4: "-target-cpu" "c86-4g-m4"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m6 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m6
+// c86-4g-m6: "-target-cpu" "c86-4g-m6"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m7 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m7
+// c86-4g-m7: "-target-cpu" "c86-4g-m7"
+
// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
// x86-64: "-target-cpu" "x86-64"
// RUN: %clang -target x86_64 -c -### %s -march=x86-64-v2 2>&1 | FileCheck %s --check-prefix=x86-64-v2
diff --git a/clang/test/Frontend/x86-target-cpu.c b/clang/test/Frontend/x86-target-cpu.c
index 7dc7f5474687e..281e41c03c4d0 100644
--- a/clang/test/Frontend/x86-target-cpu.c
+++ b/clang/test/Frontend/x86-target-cpu.c
@@ -40,5 +40,8 @@
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m4 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m7 -verify %s
//
// expected-no-diagnostics
diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c
index 766bd679796f5..921c4b7c5cab0 100644
--- a/clang/test/Misc/target-invalid-cpu-note/x86.c
+++ b/clang/test/Misc/target-invalid-cpu-note/x86.c
@@ -104,6 +104,9 @@
// X86-SAME: {{^}}, znver4
// X86-SAME: {{^}}, znver5
// X86-SAME: {{^}}, znver6
+// X86-SAME: {{^}}, c86-4g-m4
+// X86-SAME: {{^}}, c86-4g-m6
+// X86-SAME: {{^}}, c86-4g-m7
// X86-SAME: {{^}}, x86-64
// X86-SAME: {{^}}, x86-64-v2
// X86-SAME: {{^}}, x86-64-v3
@@ -185,6 +188,9 @@
// X86_64-SAME: {{^}}, znver4
// X86_64-SAME: {{^}}, znver5
// X86_64-SAME: {{^}}, znver6
+// X86_64-SAME: {{^}}, c86-4g-m4
+// X86_64-SAME: {{^}}, c86-4g-m6
+// X86_64-SAME: {{^}}, c86-4g-m7
// X86_64-SAME: {{^}}, x86-64
// X86_64-SAME: {{^}}, x86-64-v2
// X86_64-SAME: {{^}}, x86-64-v3
@@ -293,6 +299,9 @@
// TUNE_X86-SAME: {{^}}, znver4
// TUNE_X86-SAME: {{^}}, znver5
// TUNE_X86-SAME: {{^}}, znver6
+// TUNE_X86-SAME: {{^}}, c86-4g-m4
+// TUNE_X86-SAME: {{^}}, c86-4g-m6
+// TUNE_X86-SAME: {{^}}, c86-4g-m7
// TUNE_X86-SAME: {{^}}, x86-64
// TUNE_X86-SAME: {{^}}, geode
// TUNE_X86-SAME: {{$}}
@@ -399,6 +408,9 @@
// TUNE_X86_64-SAME: {{^}}, znver4
// TUNE_X86_64-SAME: {{^}}, znver5
// TUNE_X86_64-SAME: {{^}}, znver6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m4
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m7
// TUNE_X86_64-SAME: {{^}}, x86-64
// TUNE_X86_64-SAME: {{^}}, geode
// TUNE_X86_64-SAME: {{$}}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index cb2d13d59d8bf..bc950f5ecee9c 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4287,6 +4287,304 @@
// CHECK_ZNVER6_M64: #define __znver6 1
// CHECK_ZNVER6_M64: #define __znver6__ 1
+// RUN: %clang -march=c86-4g-m4 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M32
+// CHECK_C864GM4_M32: #define __ADX__ 1
+// CHECK_C864GM4_M32: #define __AES__ 1
+// CHECK_C864GM4_M32: #define __AVX2__ 1
+// CHECK_C864GM4_M32: #define __AVX__ 1
+// CHECK_C864GM4_M32: #define __BMI2__ 1
+// CHECK_C864GM4_M32: #define __BMI__ 1
+// CHECK_C864GM4_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M32: #define __CLZERO__ 1
+// CHECK_C864GM4_M32: #define __CRC32__ 1
+// CHECK_C864GM4_M32: #define __F16C__ 1
+// CHECK_C864GM4_M32: #define __FMA__ 1
+// CHECK_C864GM4_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M32: #define __FXSR__ 1
+// CHECK_C864GM4_M32: #define __LZCNT__ 1
+// CHECK_C864GM4_M32: #define __MMX__ 1
+// CHECK_C864GM4_M32: #define __MOVBE__ 1
+// CHECK_C864GM4_M32: #define __MWAITX__ 1
+// CHECK_C864GM4_M32: #define __PCLMUL__ 1
+// CHECK_C864GM4_M32: #define __POPCNT__ 1
+// CHECK_C864GM4_M32: #define __PRFCHW__ 1
+// CHECK_C864GM4_M32: #define __RDRND__ 1
+// CHECK_C864GM4_M32: #define __RDSEED__ 1
+// CHECK_C864GM4_M32: #define __SHA__ 1
+// CHECK_C864GM4_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE2__ 1
+// CHECK_C864GM4_M32: #define __SSE3__ 1
+// CHECK_C864GM4_M32: #define __SSE4A__ 1
+// CHECK_C864GM4_M32: #define __SSE4_1__ 1
+// CHECK_C864GM4_M32: #define __SSE4_2__ 1
+// CHECK_C864GM4_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE__ 1
+// CHECK_C864GM4_M32: #define __SSSE3__ 1
+// CHECK_C864GM4_M32: #define __XSAVEC__ 1
+// CHECK_C864GM4_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M32: #define __XSAVES__ 1
+// CHECK_C864GM4_M32: #define __XSAVE__ 1
+// CHECK_C864GM4_M32: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __i386 1
+// CHECK_C864GM4_M32: #define __i386__ 1
+// CHECK_C864GM4_M32: #define __tune_c86 -4g-m4__ 1
+
+// RUN: %clang -march=c86-4g-m4 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M64
+// CHECK_C864GM4_M64: #define __ADX__ 1
+// CHECK_C864GM4_M64: #define __AES__ 1
+// CHECK_C864GM4_M64: #define __AVX2__ 1
+// CHECK_C864GM4_M64: #define __AVX__ 1
+// CHECK_C864GM4_M64: #define __BMI2__ 1
+// CHECK_C864GM4_M64: #define __BMI__ 1
+// CHECK_C864GM4_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M64: #define __CLZERO__ 1
+// CHECK_C864GM4_M64: #define __CRC32__ 1
+// CHECK_C864GM4_M64: #define __F16C__ 1
+// CHECK_C864GM4_M64: #define __FMA__ 1
+// CHECK_C864GM4_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M64: #define __FXSR__ 1
+// CHECK_C864GM4_M64: #define __LZCNT__ 1
+// CHECK_C864GM4_M64: #define __MMX__ 1
+// CHECK_C864GM4_M64: #define __MOVBE__ 1
+// CHECK_C864GM4_M64: #define __MWAITX__ 1
+// CHECK_C864GM4_M64: #define __PCLMUL__ 1
+// CHECK_C864GM4_M64: #define __POPCNT__ 1
+// CHECK_C864GM4_M64: #define __PRFCHW__ 1
+// CHECK_C864GM4_M64: #define __RDRND__ 1
+// CHECK_C864GM4_M64: #define __RDSEED__ 1
+// CHECK_C864GM4_M64: #define __SHA__ 1
+// CHECK_C864GM4_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE2__ 1
+// CHECK_C864GM4_M64: #define __SSE3__ 1
+// CHECK_C864GM4_M64: #define __SSE4A__ 1
+// CHECK_C864GM4_M64: #define __SSE4_1__ 1
+// CHECK_C864GM4_M64: #define __SSE4_2__ 1
+// CHECK_C864GM4_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE__ 1
+// CHECK_C864GM4_M64: #define __SSSE3__ 1
+// CHECK_C864GM4_M64: #define __XSAVEC__ 1
+// CHECK_C864GM4_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M64: #define __XSAVES__ 1
+// CHECK_C864GM4_M64: #define __XSAVE__ 1
+// CHECK_C864GM4_M64: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __x86_64 1
+// CHECK_C864GM4_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M32
+// CHECK_C864GM6_M32: #define __ADX__ 1
+// CHECK_C864GM6_M32: #define __AES__ 1
+// CHECK_C864GM6_M32: #define __AVX2__ 1
+// CHECK_C864GM6_M32: #define __AVX__ 1
+// CHECK_C864GM6_M32: #define __BMI2__ 1
+// CHECK_C864GM6_M32: #define __BMI__ 1
+// CHECK_C864GM6_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M32: #define __CLZERO__ 1
+// CHECK_C864GM6_M32: #define __CRC32__ 1
+// CHECK_C864GM6_M32: #define __F16C__ 1
+// CHECK_C864GM6_M32: #define __FMA__ 1
+// CHECK_C864GM6_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M32: #define __FXSR__ 1
+// CHECK_C864GM6_M32: #define __LZCNT__ 1
+// CHECK_C864GM6_M32: #define __MMX__ 1
+// CHECK_C864GM6_M32: #define __MOVBE__ 1
+// CHECK_C864GM6_M32: #define __MWAITX__ 1
+// CHECK_C864GM6_M32: #define __PCLMUL__ 1
+// CHECK_C864GM6_M32: #define __POPCNT__ 1
+// CHECK_C864GM6_M32: #define __PRFCHW__ 1
+// CHECK_C864GM6_M32: #define __RDRND__ 1
+// CHECK_C864GM6_M32: #define __RDSEED__ 1
+// CHECK_C864GM6_M32: #define __SHA__ 1
+// CHECK_C864GM6_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE2__ 1
+// CHECK_C864GM6_M32: #define __SSE3__ 1
+// CHECK_C864GM6_M32: #define __SSE4A__ 1
+// CHECK_C864GM6_M32: #define __SSE4_1__ 1
+// CHECK_C864GM6_M32: #define __SSE4_2__ 1
+// CHECK_C864GM6_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE__ 1
+// CHECK_C864GM6_M32: #define __SSSE3__ 1
+// CHECK_C864GM6_M32: #define __XSAVEC__ 1
+// CHECK_C864GM6_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M32: #define __XSAVES__ 1
+// CHECK_C864GM6_M32: #define __XSAVE__ 1
+// CHECK_C864GM6_M32: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __i386 1
+// CHECK_C864GM6_M32: #define __i386__ 1
+// CHECK_C864GM6_M32: #define __tune_c86 -4g-m6__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M64
+// CHECK_C864GM6_M64: #define __ADX__ 1
+// CHECK_C864GM6_M64: #define __AES__ 1
+// CHECK_C864GM6_M64: #define __AVX2__ 1
+// CHECK_C864GM6_M64: #define __AVX__ 1
+// CHECK_C864GM6_M64: #define __BMI2__ 1
+// CHECK_C864GM6_M64: #define __BMI__ 1
+// CHECK_C864GM6_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M64: #define __CLZERO__ 1
+// CHECK_C864GM6_M64: #define __CRC32__ 1
+// CHECK_C864GM6_M64: #define __F16C__ 1
+// CHECK_C864GM6_M64: #define __FMA__ 1
+// CHECK_C864GM6_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M64: #define __FXSR__ 1
+// CHECK_C864GM6_M64: #define __LZCNT__ 1
+// CHECK_C864GM6_M64: #define __MMX__ 1
+// CHECK_C864GM6_M64: #define __MOVBE__ 1
+// CHECK_C864GM6_M64: #define __MWAITX__ 1
+// CHECK_C864GM6_M64: #define __PCLMUL__ 1
+// CHECK_C864GM6_M64: #define __POPCNT__ 1
+// CHECK_C864GM6_M64: #define __PRFCHW__ 1
+// CHECK_C864GM6_M64: #define __RDRND__ 1
+// CHECK_C864GM6_M64: #define __RDSEED__ 1
+// CHECK_C864GM6_M64: #define __SHA__ 1
+// CHECK_C864GM6_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE2__ 1
+// CHECK_C864GM6_M64: #define __SSE3__ 1
+// CHECK_C864GM6_M64: #define __SSE4A__ 1
+// CHECK_C864GM6_M64: #define __SSE4_1__ 1
+// CHECK_C864GM6_M64: #define __SSE4_2__ 1
+// CHECK_C864GM6_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE__ 1
+// CHECK_C864GM6_M64: #define __SSSE3__ 1
+// CHECK_C864GM6_M64: #define __XSAVEC__ 1
+// CHECK_C864GM6_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M64: #define __XSAVES__ 1
+// CHECK_C864GM6_M64: #define __XSAVE__ 1
+// CHECK_C864GM6_M64: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __x86_64 1
+// CHECK_C864GM6_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M32
+// CHECK_C864GM7_M32: #define __ADX__ 1
+// CHECK_C864GM7_M32: #define __AES__ 1
+// CHECK_C864GM7_M32: #define __AVX2__ 1
+// CHECK_C864GM7_M32: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M32: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M32: #define __AVX512BW__ 1
+// CHECK_C864GM7_M32: #define __AVX512CD__ 1
+// CHECK_C864GM7_M32: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M32: #define __AVX512F__ 1
+// CHECK_C864GM7_M32: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VL__ 1
+// CHECK_C864GM7_M32: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M32: #define __AVX__ 1
+// CHECK_C864GM7_M32: #define __BMI2__ 1
+// CHECK_C864GM7_M32: #define __BMI__ 1
+// CHECK_C864GM7_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M32: #define __CLWB__ 1
+// CHECK_C864GM7_M32: #define __CLZERO__ 1
+// CHECK_C864GM7_M32: #define __CRC32__ 1
+// CHECK_C864GM7_M32: #define __F16C__ 1
+// CHECK_C864GM7_M32: #define __FMA__ 1
+// CHECK_C864GM7_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M32: #define __FXSR__ 1
+// CHECK_C864GM7_M32: #define __GFNI__ 1
+// CHECK_C864GM7_M32: #define __LZCNT__ 1
+// CHECK_C864GM7_M32: #define __MMX__ 1
+// CHECK_C864GM7_M32: #define __MOVBE__ 1
+// CHECK_C864GM7_M32: #define __MWAITX__ 1
+// CHECK_C864GM7_M32: #define __PCLMUL__ 1
+// CHECK_C864GM7_M32: #define __POPCNT__ 1
+// CHECK_C864GM7_M32: #define __PRFCHW__ 1
+// CHECK_C864GM7_M32: #define __RDRND__ 1
+// CHECK_C864GM7_M32: #define __RDSEED__ 1
+// CHECK_C864GM7_M32: #define __SHA__ 1
+// CHECK_C864GM7_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE2__ 1
+// CHECK_C864GM7_M32: #define __SSE3__ 1
+// CHECK_C864GM7_M32: #define __SSE4A__ 1
+// CHECK_C864GM7_M32: #define __SSE4_1__ 1
+// CHECK_C864GM7_M32: #define __SSE4_2__ 1
+// CHECK_C864GM7_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE__ 1
+// CHECK_C864GM7_M32: #define __SSSE3__ 1
+// CHECK_C864GM7_M32: #define __VAES__ 1
+// CHECK_C864GM7_M32: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M32: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M32: #define __XSAVEC__ 1
+// CHECK_C864GM7_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M32: #define __XSAVES__ 1
+// CHECK_C864GM7_M32: #define __XSAVE__ 1
+// CHECK_C864GM7_M32: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __i386 1
+// CHECK_C864GM7_M32: #define __i386__ 1
+// CHECK_C864GM7_M32: #define __tune_c86 -4g-m7__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M64
+// CHECK_C864GM7_M64: #define __ADX__ 1
+// CHECK_C864GM7_M64: #define __AES__ 1
+// CHECK_C864GM7_M64: #define __AVX2__ 1
+// CHECK_C864GM7_M64: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M64: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M64: #define __AVX512BW__ 1
+// CHECK_C864GM7_M64: #define __AVX512CD__ 1
+// CHECK_C864GM7_M64: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M64: #define __AVX512F__ 1
+// CHECK_C864GM7_M64: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VL__ 1
+// CHECK_C864GM7_M64: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M64: #define __AVX__ 1
+// CHECK_C864GM7_M64: #define __BMI2__ 1
+// CHECK_C864GM7_M64: #define __BMI__ 1
+// CHECK_C864GM7_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M64: #define __CLWB__ 1
+// CHECK_C864GM7_M64: #define __CLZERO__ 1
+// CHECK_C864GM7_M64: #define __CRC32__ 1
+// CHECK_C864GM7_M64: #define __F16C__ 1
+// CHECK_C864GM7_M64: #define __FMA__ 1
+// CHECK_C864GM7_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M64: #define __FXSR__ 1
+// CHECK_C864GM7_M64: #define __GFNI__ 1
+// CHECK_C864GM7_M64: #define __LZCNT__ 1
+// CHECK_C864GM7_M64: #define __MMX__ 1
+// CHECK_C864GM7_M64: #define __MOVBE__ 1
+// CHECK_C864GM7_M64: #define __MWAITX__ 1
+// CHECK_C864GM7_M64: #define __PCLMUL__ 1
+// CHECK_C864GM7_M64: #define __POPCNT__ 1
+// CHECK_C864GM7_M64: #define __PRFCHW__ 1
+// CHECK_C864GM7_M64: #define __RDRND__ 1
+// CHECK_C864GM7_M64: #define __RDSEED__ 1
+// CHECK_C864GM7_M64: #define __SHA__ 1
+// CHECK_C864GM7_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE2__ 1
+// CHECK_C864GM7_M64: #define __SSE3__ 1
+// CHECK_C864GM7_M64: #define __SSE4A__ 1
+// CHECK_C864GM7_M64: #define __SSE4_1__ 1
+// CHECK_C864GM7_M64: #define __SSE4_2__ 1
+// CHECK_C864GM7_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE__ 1
+// CHECK_C864GM7_M64: #define __SSSE3__ 1
+// CHECK_C864GM7_M64: #define __VAES__ 1
+// CHECK_C864GM7_M64: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M64: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M64: #define __XSAVEC__ 1
+// CHECK_C864GM7_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M64: #define __XSAVES__ 1
+// CHECK_C864GM7_M64: #define __XSAVE__ 1
+// CHECK_C864GM7_M64: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __x86_64 1
+// CHECK_C864GM7_M64: #define __x86_64__ 1
+
// End X86/GCC/Linux tests ------------------
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index a71078e9064d5..44e0560391966 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -36,11 +36,13 @@
enum VendorSignatures {
SIG_INTEL = 0x756e6547, // Genu
SIG_AMD = 0x68747541, // Auth
+ SIG_HYGON = 0x6f677948, // Hygo
};
enum ProcessorVendors {
VENDOR_INTEL = 1,
VENDOR_AMD,
+ VENDOR_HYGON,
VENDOR_OTHER,
VENDOR_MAX
};
@@ -66,6 +68,7 @@ enum ProcessorTypes {
INTEL_GRANDRIDGE,
INTEL_CLEARWATERFOREST,
AMDFAM1AH,
+ HYGONFAM18H,
CPU_TYPE_MAX
};
@@ -108,6 +111,9 @@ enum ProcessorSubtypes {
AMDFAM1AH_ZNVER6,
INTEL_COREI7_DIAMONDRAPIDS,
INTEL_COREI7_NOVALAKE,
+ HYGONFAM18H_C86_4G_M4,
+ HYGONFAM18H_C86_4G_M6,
+ HYGONFAM18H_C86_4G_M7,
CPU_SUBTYPE_MAX
};
@@ -872,6 +878,47 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
return CPU;
}
+static const char *
+getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
+ const unsigned *Features,
+ struct __processor_model *CpuModel) {
+ const char *CPU = 0;
+
+ enum ProcessorTypes Type = CPU_TYPE_MAX;
+ enum ProcessorSubtypes Subtype = CPU_SUBTYPE_MAX;
+
+ switch (Family) {
+ case 24:
+ switch (Model) {
+ case 4:
+ CPU = "c86-4g-m4";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M4;
+ break; // c86-4g-m4
+ case 6:
+ CPU = "c86-4g-m6";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M6;
+ break; // c86-4g-m6
+ case 7:
+ CPU = "c86-4g-m7";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M7;
+ break; // c86-4g-m7
+ }
+ break; // Hygon Family 18H
+ default:
+ break; // Unknown Hygon CPU.
+ }
+
+ if (Type != CPU_TYPE_MAX)
+ CpuModel->__cpu_type = Type;
+ if (Subtype != CPU_SUBTYPE_MAX)
+ CpuModel->__cpu_subtype = Subtype;
+
+ return CPU;
+}
+
#undef testFeature
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
@@ -1235,6 +1282,9 @@ int CONSTRUCTOR_ATTRIBUT...
[truncated]
|
phoebewang
reviewed
Mar 20, 2026
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
RKSimon
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Mar 20, 2026
carlocab
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Mar 22, 2026
carlocab
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Mar 25, 2026
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Seems reasonable to me, barring the macro name bug. I'll defer to @RKSimon or @phoebewang for the ✅
Co-authored-by: Carlo Cabrera <github@carlo.cab>
phoebewang
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Mar 26, 2026
phoebewang
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Mar 26, 2026
phoebewang
approved these changes
Mar 27, 2026
RKSimon
reviewed
Mar 27, 2026
| ProcessorFeatures.C864GM4Tuning>; | ||
| def : Proc<"c86-4g-m6", ProcessorFeatures.C864GM6Features, | ||
| ProcessorFeatures.C864GM6Tuning>; | ||
| def : Proc<"c86-4g-m7", ProcessorFeatures.C864GM7Features, |
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Any thoughts to using an existing scheduler model? AFAICT M4/6 are pretty close to Znver2 and M7 is close to Znver4
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We're developing M4/M6 and M7 scheduler models now, and we'll upload them in about a month.
There are some differences between M4/M6/M7 and Znver2/Znver4, so I think we'd better not use Znver2/Znver4 scheduler models.
Contributor
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If it's close, it probably just makes sense to use znver2/znver4.
Contributor
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Yes, even if its just until you provide replacement tuned models - ideally I'd like to avoid all uses of Proc<> and always use ProcModel<> even if its just an approximation.
Author
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I have uploaded two scheduler models for c86-4g-m4, c86-4g-m6 and c86-4g-m7.
The C864GM4Model is for c86-4g-m4/m6 to use, and the C864GM7Model is for c86-4g-m7 to use.
🐧 Linux x64 Test Results
✅ The build succeeded and all tests passed. |
🪟 Windows x64 Test Results
✅ The build succeeded and all tests passed. |
RKSimon
reviewed
May 14, 2026
| //===----------------------------------------------------------------------===// | ||
|
|
||
| // The C864GM4 has 4 ALUs. | ||
| def 4GM4ALU0 : ProcResource<1>; |
Contributor
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It might not be a good idea for the prefix to start with a number - tablegen is pretty relaxed about it at the moment, but maybe not forever - could you use CGM4 and CGM7 instead?
Author
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OK, I will change it.
Author
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I have changed the prefix in the schedule model so that it no longer starts with a number. And I use the C4GM4 and C4GM7 to instead.
RKSimon
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May 15, 2026 10:59
RKSimon
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May 18, 2026
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LGTM - just fix the missing newlines in the scheduler model files
@phoebewang is there anything that we need to keep in sync with gcc?
| ], ZeroIdiomPredicate>, | ||
| ]>; | ||
|
|
||
| } // SchedModel |
Contributor
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(style) Missing newline at EOF
Author
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I have added a newline at EOF.
Contributor
The definition order in X86TargetParser.def? I actually am not sure if the current order matches though. |
Contributor
CC @boomanaiden154 @mikolaj-pirog who I think have commented on this in the past |
Member
We are out-of-sync with gcc (libgcc). I have a PR to fix that (#171172) but unfortunately I haven't yet had time to revisit this (I miss some testing and resolving conflicts, few more entries appeared since I last worked on this...) I would recommend to assign numerical values to enum entries in compiler-rt and use dummy entries for X86TargetParser to match the values. Without matching gcc on values, function multiversioning will not work with libgcc (which is the default for x86 with llvm) |
Author
|
Hi @RKSimon, I see the PR has been approved and the CI errors don't seem to be caused by this PR. Do I need to modify anything else? If not, is it ready to be merged? |
RKSimon
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Jun 1, 2026
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Relevant CI failures?
Failed Tests (4):
LLVM :: tools/llvm-mca/X86/4GM4/zero-idioms.s
LLVM :: tools/llvm-mca/X86/4GM7/independent-load-stores.s
LLVM :: tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
LLVM :: tools/llvm-mca/X86/4GM7/zero-idioms.s
Also, please can you update those folder names not to have a leading numeric (C864GM* instead?)
Change-Id: I8c09ab1c5652a1980a3d0b640f93a8eb2dca5058
RKSimon
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Jun 5, 2026
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LGTM - although we REALLY need to get X86TargetParser.def etc. synced with libgcc again before 23.x
Author
Hi @RKSimon , I think this PR is ready to be merged. Could you please help merge it when you have a moment? Thanks! |
RKSimon
enabled auto-merge (squash)
June 9, 2026 10:09
|
@zhangxiaomeng-hygon Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR. Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues. How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
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Jun 11, 2026
This patch adds initial support for several Hygon architectures. The Hygon architectures include: - c86-4g-m4 - c86-4g-m6 - c86-4g-m7 This patch includes: - Added Hygon architectures CPU targets recognition in Clang and LLVM - Added Hygon architectures to target parser and host CPU detection - Updated compiler-rt CPU model detection for Hygon architectures - Added Hygon architectures to various optimizer tests - Added scheduler models for Hygon architectures CPU targets
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This patch adds initial support for several Hygon architectures.
The Hygon architectures include:
This patch includes: