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[X86] AMD Zen 6 Initial enablement #179150

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Merged
ganeshgit merged 1 commit into from
Feb 7, 2026
Merged

[X86] AMD Zen 6 Initial enablement #179150

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1 change: 1 addition & 0 deletions clang/docs/ReleaseNotes.rst
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Expand Up @@ -265,6 +265,7 @@ NVPTX Support

X86 Support
^^^^^^^^^^^
- ``march=znver6`` is now supported.

Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
Expand Down
4 changes: 4 additions & 0 deletions clang/lib/Basic/Targets/X86.cpp
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Expand Up @@ -716,6 +716,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_ZNVER5:
defineCPUMacros(Builder, "znver5");
break;
case CK_ZNVER6:
defineCPUMacros(Builder, "znver6");
break;
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
Expand Down Expand Up @@ -1641,6 +1644,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER3:
case CK_ZNVER4:
case CK_ZNVER5:
case CK_ZNVER6:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
Expand Down
1 change: 1 addition & 0 deletions clang/test/CodeGen/target-builtin-noerror.c
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Expand Up @@ -209,5 +209,6 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver3");
(void)__builtin_cpu_is("znver4");
(void)__builtin_cpu_is("znver5");
(void)__builtin_cpu_is("znver6");
(void)__builtin_cpu_is("diamondrapids");
}
4 changes: 4 additions & 0 deletions clang/test/Driver/x86-march.c
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Expand Up @@ -258,6 +258,10 @@
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver5 2>&1 \
// RUN: | FileCheck %s -check-prefix=znver5
// znver5: "-target-cpu" "znver5"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver6 2>&1 \
// RUN: | FileCheck %s -check-prefix=znver6
// znver6: "-target-cpu" "znver6"

// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
// x86-64: "-target-cpu" "x86-64"
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1 change: 1 addition & 0 deletions clang/test/Frontend/x86-target-cpu.c
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Expand Up @@ -39,5 +39,6 @@
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver6 -verify %s
//
// expected-no-diagnostics
4 changes: 4 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/x86.c
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Expand Up @@ -103,6 +103,7 @@
// X86-SAME: {{^}}, znver3
// X86-SAME: {{^}}, znver4
// X86-SAME: {{^}}, znver5
// X86-SAME: {{^}}, znver6
// X86-SAME: {{^}}, x86-64
// X86-SAME: {{^}}, x86-64-v2
// X86-SAME: {{^}}, x86-64-v3
Expand Down Expand Up @@ -183,6 +184,7 @@
// X86_64-SAME: {{^}}, znver3
// X86_64-SAME: {{^}}, znver4
// X86_64-SAME: {{^}}, znver5
// X86_64-SAME: {{^}}, znver6
// X86_64-SAME: {{^}}, x86-64
// X86_64-SAME: {{^}}, x86-64-v2
// X86_64-SAME: {{^}}, x86-64-v3
Expand Down Expand Up @@ -290,6 +292,7 @@
// TUNE_X86-SAME: {{^}}, znver3
// TUNE_X86-SAME: {{^}}, znver4
// TUNE_X86-SAME: {{^}}, znver5
// TUNE_X86-SAME: {{^}}, znver6
// TUNE_X86-SAME: {{^}}, x86-64
// TUNE_X86-SAME: {{^}}, geode
// TUNE_X86-SAME: {{$}}
Expand Down Expand Up @@ -395,6 +398,7 @@
// TUNE_X86_64-SAME: {{^}}, znver3
// TUNE_X86_64-SAME: {{^}}, znver4
// TUNE_X86_64-SAME: {{^}}, znver5
// TUNE_X86_64-SAME: {{^}}, znver6
// TUNE_X86_64-SAME: {{^}}, x86-64
// TUNE_X86_64-SAME: {{^}}, geode
// TUNE_X86_64-SAME: {{$}}
151 changes: 151 additions & 0 deletions clang/test/Preprocessor/predefined-arch-macros.c
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Expand Up @@ -4133,6 +4133,157 @@
// CHECK_ZNVER5_M64: #define __znver5 1
// CHECK_ZNVER5_M64: #define __znver5__ 1

// RUN: %clang -march=znver6 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER6_M32
// CHECK_ZNVER6_M32-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER6_M32-NOT: #define __3dNOW__ 1
// CHECK_ZNVER6_M32: #define __ADX__ 1
// CHECK_ZNVER6_M32: #define __AES__ 1
// CHECK_ZNVER6_M32: #define __AVX2__ 1
// CHECK_ZNVER6_M32: #define __AVX512BF16__ 1
// CHECK_ZNVER6_M32: #define __AVX512BITALG__ 1
// CHECK_ZNVER6_M32: #define __AVX512BW__ 1
// CHECK_ZNVER6_M32: #define __AVX512CD__ 1
// CHECK_ZNVER6_M32: #define __AVX512DQ__ 1
// CHECK_ZNVER6_M32: #define __AVX512FP16__ 1
// CHECK_ZNVER6_M32: #define __AVX512F__ 1
// CHECK_ZNVER6_M32: #define __AVX512IFMA__ 1
// CHECK_ZNVER6_M32: #define __AVX512VBMI2__ 1
// CHECK_ZNVER6_M32: #define __AVX512VBMI__ 1
// CHECK_ZNVER6_M32: #define __AVX512VL__ 1
// CHECK_ZNVER6_M32: #define __AVX512VNNI__ 1
// CHECK_ZNVER6_M32: #define __AVX512VP2INTERSECT__ 1
// CHECK_ZNVER6_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ZNVER6_M32: #define __AVXIFMA__ 1
// CHECK_ZNVER6_M32: #define __AVXNECONVERT__ 1
// CHECK_ZNVER6_M32: #define __AVXVNNIINT8__ 1
// CHECK_ZNVER6_M32: #define __AVXVNNI__ 1
// CHECK_ZNVER6_M32: #define __AVX__ 1
// CHECK_ZNVER6_M32: #define __BMI2__ 1
// CHECK_ZNVER6_M32: #define __BMI__ 1
// CHECK_ZNVER6_M32: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER6_M32: #define __CLWB__ 1
// CHECK_ZNVER6_M32: #define __CLZERO__ 1
// CHECK_ZNVER6_M32: #define __F16C__ 1
// CHECK_ZNVER6_M32-NOT: #define __FMA4__ 1
// CHECK_ZNVER6_M32: #define __FMA__ 1
// CHECK_ZNVER6_M32: #define __FSGSBASE__ 1
// CHECK_ZNVER6_M32: #define __GFNI__ 1
// CHECK_ZNVER6_M32: #define __LZCNT__ 1
// CHECK_ZNVER6_M32: #define __MMX__ 1
// CHECK_ZNVER6_M32: #define __MOVDIR64B__ 1
// CHECK_ZNVER6_M32: #define __MOVDIRI__ 1
// CHECK_ZNVER6_M32: #define __PCLMUL__ 1
// CHECK_ZNVER6_M32: #define __PKU__ 1
// CHECK_ZNVER6_M32: #define __POPCNT__ 1
// CHECK_ZNVER6_M32: #define __PREFETCHI__ 1
// CHECK_ZNVER6_M32: #define __PRFCHW__ 1
// CHECK_ZNVER6_M32: #define __RDPID__ 1
// CHECK_ZNVER6_M32: #define __RDPRU__ 1
// CHECK_ZNVER6_M32: #define __RDRND__ 1
// CHECK_ZNVER6_M32: #define __RDSEED__ 1
// CHECK_ZNVER6_M32: #define __SHA__ 1
// CHECK_ZNVER6_M32: #define __SSE2_MATH__ 1
// CHECK_ZNVER6_M32: #define __SSE2__ 1
// CHECK_ZNVER6_M32: #define __SSE3__ 1
// CHECK_ZNVER6_M32: #define __SSE4A__ 1
// CHECK_ZNVER6_M32: #define __SSE4_1__ 1
// CHECK_ZNVER6_M32: #define __SSE4_2__ 1
// CHECK_ZNVER6_M32: #define __SSE_MATH__ 1
// CHECK_ZNVER6_M32: #define __SSE__ 1
// CHECK_ZNVER6_M32: #define __SSSE3__ 1
// CHECK_ZNVER6_M32-NOT: #define __TBM__ 1
// CHECK_ZNVER6_M32: #define __WBNOINVD__ 1
// CHECK_ZNVER6_M32-NOT: #define __XOP__ 1
// CHECK_ZNVER6_M32: #define __XSAVEC__ 1
// CHECK_ZNVER6_M32: #define __XSAVEOPT__ 1
// CHECK_ZNVER6_M32: #define __XSAVES__ 1
// CHECK_ZNVER6_M32: #define __XSAVE__ 1
// CHECK_ZNVER6_M32: #define __i386 1
// CHECK_ZNVER6_M32: #define __i386__ 1
// CHECK_ZNVER6_M32: #define __tune_znver6__ 1
// CHECK_ZNVER6_M32: #define __znver6 1
// CHECK_ZNVER6_M32: #define __znver6__ 1

// RUN: %clang -march=znver6 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER6_M64
// CHECK_ZNVER6_M64-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER6_M64-NOT: #define __3dNOW__ 1
// CHECK_ZNVER6_M64: #define __ADX__ 1
// CHECK_ZNVER6_M64: #define __AES__ 1
// CHECK_ZNVER6_M64: #define __AVX2__ 1
// CHECK_ZNVER6_M64: #define __AVX512BF16__ 1
// CHECK_ZNVER6_M64: #define __AVX512BITALG__ 1
// CHECK_ZNVER6_M64: #define __AVX512BW__ 1
// CHECK_ZNVER6_M64: #define __AVX512CD__ 1
// CHECK_ZNVER6_M64: #define __AVX512DQ__ 1
// CHECK_ZNVER6_M64: #define __AVX512FP16__ 1
// CHECK_ZNVER6_M64: #define __AVX512F__ 1
// CHECK_ZNVER6_M64: #define __AVX512IFMA__ 1
// CHECK_ZNVER6_M64: #define __AVX512VBMI2__ 1
// CHECK_ZNVER6_M64: #define __AVX512VBMI__ 1
// CHECK_ZNVER6_M64: #define __AVX512VL__ 1
// CHECK_ZNVER6_M64: #define __AVX512VNNI__ 1
// CHECK_ZNVER6_M64: #define __AVX512VP2INTERSECT__ 1
// CHECK_ZNVER6_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ZNVER6_M64: #define __AVXIFMA__ 1
// CHECK_ZNVER6_M64: #define __AVXNECONVERT__ 1
// CHECK_ZNVER6_M64: #define __AVXVNNIINT8__ 1
// CHECK_ZNVER6_M64: #define __AVXVNNI__ 1
// CHECK_ZNVER6_M64: #define __AVX__ 1
// CHECK_ZNVER6_M64: #define __BMI2__ 1
// CHECK_ZNVER6_M64: #define __BMI__ 1
// CHECK_ZNVER6_M64: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER6_M64: #define __CLWB__ 1
// CHECK_ZNVER6_M64: #define __CLZERO__ 1
// CHECK_ZNVER6_M64: #define __F16C__ 1
// CHECK_ZNVER6_M64-NOT: #define __FMA4__ 1
// CHECK_ZNVER6_M64: #define __FMA__ 1
// CHECK_ZNVER6_M64: #define __FSGSBASE__ 1
// CHECK_ZNVER6_M64: #define __GFNI__ 1
// CHECK_ZNVER6_M64: #define __LZCNT__ 1
// CHECK_ZNVER6_M64: #define __MMX__ 1
// CHECK_ZNVER6_M64: #define __MOVDIR64B__ 1
// CHECK_ZNVER6_M64: #define __MOVDIRI__ 1
// CHECK_ZNVER6_M64: #define __PCLMUL__ 1
// CHECK_ZNVER6_M64: #define __PKU__ 1
// CHECK_ZNVER6_M64: #define __POPCNT__ 1
// CHECK_ZNVER6_M64: #define __PREFETCHI__ 1
// CHECK_ZNVER6_M64: #define __PRFCHW__ 1
// CHECK_ZNVER6_M64: #define __RDPID__ 1
// CHECK_ZNVER6_M64: #define __RDPRU__ 1
// CHECK_ZNVER6_M64: #define __RDRND__ 1
// CHECK_ZNVER6_M64: #define __RDSEED__ 1
// CHECK_ZNVER6_M64: #define __SHA__ 1
// CHECK_ZNVER6_M64: #define __SSE2_MATH__ 1
// CHECK_ZNVER6_M64: #define __SSE2__ 1
// CHECK_ZNVER6_M64: #define __SSE3__ 1
// CHECK_ZNVER6_M64: #define __SSE4A__ 1
// CHECK_ZNVER6_M64: #define __SSE4_1__ 1
// CHECK_ZNVER6_M64: #define __SSE4_2__ 1
// CHECK_ZNVER6_M64: #define __SSE_MATH__ 1
// CHECK_ZNVER6_M64: #define __SSE__ 1
// CHECK_ZNVER6_M64: #define __SSSE3__ 1
// CHECK_ZNVER6_M64-NOT: #define __TBM__ 1
// CHECK_ZNVER6_M64: #define __VAES__ 1
// CHECK_ZNVER6_M64: #define __VPCLMULQDQ__ 1
// CHECK_ZNVER6_M64: #define __WBNOINVD__ 1
// CHECK_ZNVER6_M64-NOT: #define __XOP__ 1
// CHECK_ZNVER6_M64: #define __XSAVEC__ 1
// CHECK_ZNVER6_M64: #define __XSAVEOPT__ 1
// CHECK_ZNVER6_M64: #define __XSAVES__ 1
// CHECK_ZNVER6_M64: #define __XSAVE__ 1
// CHECK_ZNVER6_M64: #define __amd64 1
// CHECK_ZNVER6_M64: #define __amd64__ 1
// CHECK_ZNVER6_M64: #define __tune_znver6__ 1
// CHECK_ZNVER6_M64: #define __x86_64 1
// CHECK_ZNVER6_M64: #define __x86_64__ 1
// CHECK_ZNVER6_M64: #define __znver6 1
// CHECK_ZNVER6_M64: #define __znver6__ 1


// End X86/GCC/Linux tests ------------------

// Begin PPC/GCC/Linux tests ----------------
Expand Down
12 changes: 10 additions & 2 deletions compiler-rt/lib/builtins/cpu_model/x86.c
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Expand Up @@ -105,6 +105,7 @@ enum ProcessorSubtypes {
INTEL_COREI7_ARROWLAKE_S,
INTEL_COREI7_PANTHERLAKE,
AMDFAM1AH_ZNVER5,
AMDFAM1AH_ZNVER6,

@mikolaj-pirog mikolaj-pirog Feb 9, 2026

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Values in this enum have to be synced with analogous enum in libgcc. In GCC (gcc/common/config/i386/i386-cpuinfo.h) in enum processor_subtypes AMDFAM1AH_ZNVER6 has different value than here (it's after novalake). Entry in X86TargetParser.def would need to be adjusted to match the one here

The table is out-of-sync between gcc and llvm anyway, I have a PR #171172 to sync it and make it more robust, I hope to get around to having it merged soon

INTEL_COREI7_DIAMONDRAPIDS,
INTEL_COREI7_NOVALAKE,
CPU_SUBTYPE_MAX
Expand Down Expand Up @@ -837,20 +838,27 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
case 26:
CPU = "znver5";
Type = AMDFAM1AH;
if (Model <= 0x77) {
if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) ||
(Model >= 0xd0 && Model <= 0xd7)) {

@boomanaiden154 boomanaiden154 Feb 2, 2026

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Why are we removing the model comments here?

@ganeshgit ganeshgit Feb 3, 2026

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Weisshorn is excluded and we have few models included as well. The model numbers are broader now.

@RKSimon RKSimon Feb 3, 2026

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So update the comments to match Host.cpp?

// Models 00h-0Fh (Breithorn).
// Models 10h-1Fh (Breithorn-Dense).
// Models 20h-2Fh (Strix 1).
// Models 30h-37h (Strix 2).
// Models 38h-3Fh (Strix 3).
// Models 40h-4Fh (Granite Ridge).
// Models 50h-5Fh (Weisshorn).
// Models 60h-6Fh (Krackan1).
// Models 70h-77h (Sarlak).
// Models D0h-D7h (Annapurna).
CPU = "znver5";
Subtype = AMDFAM1AH_ZNVER5;
break; // "znver5"
}
if ((Model >= 0x50 && Model <= 0x5f) || (Model >= 0x80 && Model <= 0xcf) ||
(Model >= 0xd8 && Model <= 0xe7)) {
CPU = "znver6";
Subtype = AMDFAM1AH_ZNVER6;
break; // "znver6"
}
break;
default:
break; // Unknown AMD CPU.
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.def
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Expand Up @@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake")
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s")
X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER6, "znver6")
X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids")
X86_CPU_SUBTYPE(INTEL_COREI7_NOVALAKE, "novalake")

Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.h
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Expand Up @@ -146,6 +146,7 @@ enum CPUKind {
CK_ZNVER3,
CK_ZNVER4,
CK_ZNVER5,
CK_ZNVER6,
CK_x86_64,
CK_x86_64_v2,
CK_x86_64_v3,
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/X86/X86.td
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Expand Up @@ -1631,6 +1631,15 @@ def ProcessorFeatures {
];
list<SubtargetFeature> ZN5Features =
!listconcat(ZN4Features, ZN5AdditionalFeatures);

list<SubtargetFeature> ZN6Tuning = ZN5Tuning;
list<SubtargetFeature> ZN6AdditionalFeatures = [FeatureFP16,
FeatureAVXVNNIINT8,
FeatureAVXNECONVERT,
FeatureAVXIFMA
];
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1993,6 +2002,8 @@ def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,
ProcessorFeatures.ZN4Tuning>;
def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,
ProcessorFeatures.ZN5Tuning>;
def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
ProcessorFeatures.ZN6Tuning>;

def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/X86/X86PfmCounters.td
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Expand Up @@ -387,3 +387,4 @@ def ZnVer4PfmCounters : ProcPfmCounters {
}
def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;
def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>;
def : PfmCountersBinding<"znver6", ZnVer4PfmCounters>;
6 changes: 6 additions & 0 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -1340,6 +1340,12 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
*Subtype = X86::AMDFAM1AH_ZNVER5;
break; // "znver5"
}
if ((Model >= 0x50 && Model <= 0x5f) || (Model >= 0x80 && Model <= 0xcf) ||
(Model >= 0xd8 && Model <= 0xe7)) {
CPU = "znver6";
*Subtype = X86::AMDFAM1AH_ZNVER6;
break; // "znver6"
}
break;

default:
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/TargetParser/X86TargetParser.cpp
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Expand Up @@ -255,6 +255,10 @@ static constexpr FeatureBitset FeaturesZNVER5 =
FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;

static constexpr FeatureBitset FeaturesZNVER6 =
FeaturesZNVER5 | FeatureAVXVNNIINT8 | FeatureAVX512FP16 | FeatureAVXIFMA |
FeatureAVXNECONVERT;

// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
Expand Down Expand Up @@ -440,6 +444,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
{ {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/bypass-slow-division-64.ll
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Expand Up @@ -24,6 +24,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ

; Additional tests for 64-bit divide bypass

Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/cmp16.ll
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=X64,X64-FAST

define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) {
; X86-GENERIC-LABEL: cmp16_reg_eq_reg:
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/cpus-amd.ll
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Expand Up @@ -30,6 +30,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver6 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

define void @foo() {
ret void
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/rdpru.ll
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Expand Up @@ -7,6 +7,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 -fast-isel | FileCheck %s --check-prefix=X64

define void @rdpru_asm() {
; X86-LABEL: rdpru_asm:
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/shuffle-as-shifts.ll
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4


define <4 x i32> @shuf_rot_v4i32_1032(<4 x i32> %x) {
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