[GISel] computeKnownBits - add CTLS handling

llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

@@ -681,6 +681,18 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     Known.Zero.setBitsFrom(LowBits);
     break;
   }
+  case TargetOpcode::G_CTLS: {
+    auto Reg = MI.getOperand(1).getReg();
+    unsigned MinRedundantSignBits = computeNumSignBits(Reg, Depth + 1) - 1;
+
+    unsigned MaxUpperRedundantSignBits = MRI.getType(Reg).getScalarSizeInBits();
+
+    ConstantRange Range(APInt(BitWidth, MinRedundantSignBits),
+                        APInt(BitWidth, MaxUpperRedundantSignBits));
+
+    Known = Range.toKnownBits();
+    break;
+  }
   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
     GExtractVectorElement &Extract = cast<GExtractVectorElement>(MI);
     Register InVec = Extract.getVectorReg();

llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir

@@ -0,0 +1,195 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name:            CTLSConst8AmbigousMaxSignbitNum
+body:             |
+  bb.1:
+  ; NOTE: Currently we do not estimate max sign bits in KnownBits,
+  ; so while we could get more accurate here, this is currently
+  ; not possible.
+  ; CHECK-LABEL: name: @CTLSConst8AmbigousMaxSignbitNum
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00110000 SignBits:2
+  ; CHECK-NEXT: %2:_ KnownBits:00001000 SignBits:4
+  ; CHECK-NEXT: %3:_ KnownBits:00??0000 SignBits:2
+  ; CHECK-NEXT: %4:_ KnownBits:00??1000 SignBits:2
+  ; CHECK-NEXT: %5:_ KnownBits:00000??? SignBits:5
+    %0:_(s8) = COPY $b0
+    %1:_(s8) = G_CONSTANT i8 48
+    %2:_(s8) = G_CONSTANT i8 8
+    %3:_(s8) = G_AND %0, %1
+    %4:_(s8) = G_OR %3, %2
+    %5:_(s8) = G_CTLS %4
+...
+
+---
+name:            CTLSNoKnown8
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSNoKnown8
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000??? SignBits:13
+    %0:_(s8) = COPY $b0
+    %1:_(s16) = G_CTLS %0
+...
+
+---
+name:            CTLSNoKnown16
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSNoKnown16
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:000000000000???? SignBits:12
+    %0:_(s16) = COPY $h0
+    %1:_(s16) = G_CTLS %0
+...
+
+---
+name:            CTLSNoKnown32
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSNoKnown32
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000000000????? SignBits:11
+    %0:_(s32) = COPY $s0
+    %1:_(s16) = G_CTLS %0
+...
+
+
+---
+name:            CTLSHalfKnown8
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSHalfKnown8
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+  ; CHECK-NEXT: %2:_ KnownBits:00000?00 SignBits:5
+  ; CHECK-NEXT: %3:_ KnownBits:000001?? SignBits:5
+    %0:_(s8) = COPY $b0
+    %1:_(s8) = G_CONSTANT i8 4
+    %2:_(s8) = G_AND %0, %1
+    %3:_(s8) = G_CTLS %2
+...
+
+---
+name:            CTLSHalfKnown16
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSHalfKnown16
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000001000000 SignBits:9
+  ; CHECK-NEXT: %2:_ KnownBits:000000000?000000 SignBits:9
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000001??? SignBits:12
+    %0:_(s16) = COPY $h0
+    %1:_(s16) = G_CONSTANT i16 64
+    %2:_(s16) = G_AND %0, %1
+    %3:_(s16) = G_CTLS %2
+...
+
+---
+name:            CTLSHalfConst8Zero
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSHalfConst8Zero
+  ; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8
+  ; CHECK-NEXT: %1:_ KnownBits:00000111 SignBits:5
+    %0:_(s8) = G_CONSTANT i8 0
+    %1:_(s8) = G_CTLS %0
+...
+
+---
+name:            CTLSHalfConst16Zero
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSHalfConst16Zero
+  ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000001111 SignBits:12
+    %0:_(s16) = G_CONSTANT i16 0
+    %1:_(s16) = G_CTLS %0
+...
+
+---
+name:            VectorCTLSConst16Zero
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCTLSConst16Zero
+  ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000000 SignBits:16
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000001111 SignBits:12
+    %0:_(s16) = G_CONSTANT i16 0
+    %1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+    %3:_(<4 x s16>) = G_CTLS %1
+...
+
+---
+name:            VectorCTLSNoneKnown
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCTLSNoneKnown
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000001000 SignBits:12
+  ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %5:_ KnownBits:000000000000???? SignBits:12
+    %0:_(s16) = COPY $h0
+    %1:_(s16) = G_CONSTANT i16 8
+    %2:_(s16) = G_ASHR %0, %1
+    %3:_(s16) = COPY $h1
+    %4:_(<4 x s16>) = G_BUILD_VECTOR %2, %3, %2, %3
+    %5:_(<4 x s16>) = G_CTLS %4
+...
+
+---
+name:            VectorCTLSHighBitKnown
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCTLSHighBitKnown
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000001000 SignBits:12
+  ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %4:_ KnownBits:0000000000001010 SignBits:12
+  ; CHECK-NEXT: %5:_ KnownBits:000000000000???? SignBits:12
+  ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %7:_ KnownBits:0000000000001??? SignBits:12
+    %0:_(s16) = COPY $h0
+    %1:_(s16) = G_CONSTANT i16 8
+    %2:_(s16) = G_ASHR %0, %1
+    %3:_(s16) = COPY $h1
+    %4:_(s16) = G_CONSTANT i16 10
+    %5:_(s16) = G_ASHR %4, %5
+    %6:_(<4 x s16>) = G_BUILD_VECTOR %2, %5, %2, %4
+    %7:_(<4 x s16>) = G_CTLS %6
+...
+
+---
+name:            CTLSLargeEnough
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSLargeEnough
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000010000 SignBits:27
+  ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:17
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000000000000000000001???? SignBits:27
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = G_CONSTANT i32 16
+    %2:_(s32) = G_ASHR %0, %1
+    %3:_(s32) = G_CTLS %2
+...
+
+---
+name:            CTLSTooSmallToTrigger
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CTLSTooSmallToTrigger
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001111 SignBits:28
+  ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:16
+  ; CHECK-NEXT: %3:_ KnownBits:000000000000000000000000000????? SignBits:27
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = G_CONSTANT i32 15
+    %2:_(s32) = G_ASHR %0, %1
+    %3:_(s32) = G_CTLS %2
+...

llvm/test/CodeGen/AArch64/cls.ll

@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 |  FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; @llvm.aarch64.cls must be directly translated into the 'cls' instruction
 
@@ -72,12 +73,22 @@ define i32 @cls_i32_knownbits_2(i16 signext %x) {
 ; Check that the range max in ctls cls knownbits
 ; is not set to 32
 define i64 @cls_i64_not_32(i64 %x) {
-; CHECK-LABEL: cls_i64_not_32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr x8, x0, #16
-; CHECK-NEXT:    cls x8, x8
-; CHECK-NEXT:    orr x0, x8, #0x10
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: cls_i64_not_32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr x8, x0, #16
+; CHECK-SD-NEXT:    cls x8, x8
+; CHECK-SD-NEXT:    orr x0, x8, #0x10
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: cls_i64_not_32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    asr x8, x0, #63
+; CHECK-GI-NEXT:    eor x8, x8, x0, asr #16
+; CHECK-GI-NEXT:    lsl x8, x8, #1
+; CHECK-GI-NEXT:    orr x8, x8, #0x1
+; CHECK-GI-NEXT:    clz x8, x8
+; CHECK-GI-NEXT:    orr x0, x8, #0x10
+; CHECK-GI-NEXT:    ret
   %val = ashr i64 %x, 16
   %a = ashr i64 %val, 63
   %b = xor i64 %val, %a
@@ -125,12 +136,21 @@ define i32 @cls_i32_knownbits_4(i32 signext %x) {
 ; Negative test. Check that the number of sign bits is not
 ; overestimated. If it is, the orr disappears.
 define i32 @cls_i32_knownbits_no_overestimate(i32 signext %x) {
-; CHECK-LABEL: cls_i32_knownbits_no_overestimate:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #15
-; CHECK-NEXT:    cls w8, w8
-; CHECK-NEXT:    orr w0, w8, #0x10
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: cls_i32_knownbits_no_overestimate:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #15
+; CHECK-SD-NEXT:    cls w8, w8
+; CHECK-SD-NEXT:    orr w0, w8, #0x10
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: cls_i32_knownbits_no_overestimate:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    asr w8, w0, #31
+; CHECK-GI-NEXT:    eor w8, w8, w0, asr #15
+; CHECK-GI-NEXT:    clz w8, w8
+; CHECK-GI-NEXT:    sub w8, w8, #1
+; CHECK-GI-NEXT:    orr w0, w8, #0x10
+; CHECK-GI-NEXT:    ret
   %ashr = ashr i32 %x, 15
   %a = ashr i32 %ashr, 31
   %b = xor i32 %ashr, %a

llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll

@@ -139,3 +139,88 @@ define i64 @cls_i64_2(i64 %x) {
   %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true)
   ret i64 %e
 }
+
+; The result is in the range [1-31], so we don't need an andi after the cls.
+define i32 @cls_i32_knownbits(i32 %x) {
+; CHECK-LABEL: cls_i32_knownbits:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cls a0, a0
+; CHECK-NEXT:    ret
+  %a = ashr i32 %x, 31
+  %b = xor i32 %x, %a
+  %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
+  %d = sub i32 %c, 1
+  %e = and i32 %d, 31
+  ret i32 %e
+}
+
+; There are at least 16 redundant sign bits so we don't need an ori after the clsw.
+define i32 @cls_i32_knownbits_2(i16 signext %x) {
+; CHECK-LABEL: cls_i32_knownbits_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cls a0, a0
+; CHECK-NEXT:    ret
+  %sext = sext i16 %x to i32
+  %a = ashr i32 %sext, 31
+  %b = xor i32 %sext, %a
+  %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
+  %d = sub i32 %c, 1
+  %e = or i32 %d, 16
+  ret i32 %e
+}
+
+; There are at least 24 redundant sign bits so we don't need an ori after the clsw.
+define i32 @cls_i32_knownbits_3(i8 signext %x) {
+; CHECK-LABEL: cls_i32_knownbits_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cls a0, a0
+; CHECK-NEXT:    ret
+  %sext = sext i8 %x to i32
+  %a = ashr i32 %sext, 31
+  %b = xor i32 %sext, %a
+  %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
+  %d = sub i32 %c, 1
+  %e = or i32 %d, 24
+  ret i32 %e
+}
+
+; Negative test. We only know there is at least 1 redundant sign bit. We can't
+; remove the ori.
+define i32 @cls_i32_knownbits_4(i32 signext %x) {
+; CHECK-LABEL: cls_i32_knownbits_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    srai a0, a0, 1
+; CHECK-NEXT:    cls a0, a0
+; CHECK-NEXT:    ori a0, a0, 1
+; CHECK-NEXT:    ret
+  %shl = shl i32 %x, 1
+  %ashr = ashr i32 %shl, 1
+  %a = ashr i32 %ashr, 31
+  %b = xor i32 %ashr, %a
+  %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
+  %d = sub i32 %c, 1
+  %e = or i32 %d, 1
+  ret i32 %e
+ }
+
+; Negative test. Check that the number of sign bits is not
+; overestimated. If it is, the ori disappears.
+define i32 @cls_i32_knownbits_no_overestimate(i32 signext %x) {
+; CHECK-LABEL: cls_i32_knownbits_no_overestimate:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srai a1, a0, 15
+; CHECK-NEXT:    srai a0, a0, 31
+; CHECK-NEXT:    xor a0, a1, a0
+; CHECK-NEXT:    clz a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ori a0, a0, 16
+; CHECK-NEXT:    ret
+  %ashr = ashr i32 %x, 15
+  %a = ashr i32 %ashr, 31
+  %b = xor i32 %ashr, %a
+  %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
+  %d = sub i32 %c, 1
+  %e = or i32 %d, 16
+  ret i32 %e
+ }

llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll

@@ -112,3 +112,26 @@ define i64 @cls_i64_2(i64 %x) {
   %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true)
   ret i64 %e
 }
+
+; Check that the range max in ctls cls knownbits
+; is not set to 32. If it is, then ori disappears.
+define i64 @cls_i64_not_32(i64 %x) {
+; CHECK-LABEL: cls_i64_not_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srai a1, a0, 16
+; CHECK-NEXT:    srai a0, a0, 63
+; CHECK-NEXT:    xor a0, a1, a0
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    ori a0, a0, 1
+; CHECK-NEXT:    clz a0, a0
+; CHECK-NEXT:    ori a0, a0, 16
+; CHECK-NEXT:    ret
+  %val = ashr i64 %x, 16
+  %a = ashr i64 %val, 63
+  %b = xor i64 %val, %a
+  %c = shl i64 %b, 1
+  %d = or i64 %c, 1
+  %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true)
+  %f = or i64 %e, 16
+  ret i64 %f
+}