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[AArch64] Generalize CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) transform to peephole#167527

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RKSimon merged 3 commits intollvm:mainfrom
SiliconA-Z:ede-part-3
Nov 13, 2025
Merged

[AArch64] Generalize CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) transform to peephole#167527
RKSimon merged 3 commits intollvm:mainfrom
SiliconA-Z:ede-part-3

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@SiliconA-Z SiliconA-Z commented Nov 11, 2025

This transform should have never been done in ISel in the first place. It should have been done in peephole, but a few cases were missing.

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llvmbot commented Nov 11, 2025

@llvm/pr-subscribers-backend-aarch64

Author: AZero13 (AZero13)

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This transform should have never been done in ISel in the first place. It should have been done in peephole, but a few cases were missing.

Patch is 21.76 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/167527.diff

4 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (-23)
  • (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+12)
  • (modified) llvm/test/CodeGen/AArch64/alias_mask.ll (+104-110)
  • (removed) llvm/test/CodeGen/AArch64/csel-subs-dag-combine.ll (-112)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8457f6178fdc2..a4cca60cc3447 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26108,29 +26108,6 @@ static SDValue performCSELCombine(SDNode *N,
     }
   }
 
-  // CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) if cc doesn't
-  // use overflow flags, to avoid the comparison with zero. In case of success,
-  // this also replaces the original SUB(x,y) with the newly created SUBS(x,y).
-  // NOTE: Perhaps in the future use performFlagSettingCombine to replace SUB
-  // nodes with their SUBS equivalent as is already done for other flag-setting
-  // operators, in which case doing the replacement here becomes redundant.
-  if (Cond.getOpcode() == AArch64ISD::SUBS && Cond->hasNUsesOfValue(1, 1) &&
-      isNullConstant(Cond.getOperand(1))) {
-    SDValue Sub = Cond.getOperand(0);
-    AArch64CC::CondCode CC =
-        static_cast<AArch64CC::CondCode>(N->getConstantOperandVal(2));
-    if (Sub.getOpcode() == ISD::SUB &&
-        (CC == AArch64CC::EQ || CC == AArch64CC::NE || CC == AArch64CC::MI ||
-         CC == AArch64CC::PL)) {
-      SDLoc DL(N);
-      SDValue Subs = DAG.getNode(AArch64ISD::SUBS, DL, Cond->getVTList(),
-                                 Sub.getOperand(0), Sub.getOperand(1));
-      DCI.CombineTo(Sub.getNode(), Subs);
-      DCI.CombineTo(Cond.getNode(), Subs, Subs.getValue(1));
-      return SDValue(N, 0);
-    }
-  }
-
   // CSEL (LASTB P, Z), X, NE(ANY P) -> CLASTB P, X, Z
   if (SDValue CondLast = foldCSELofLASTB(N, DAG))
     return CondLast;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index b93e562f4cee5..67ee5b6636cec 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1776,10 +1776,14 @@ static unsigned sForm(MachineInstr &Instr) {
   case AArch64::ADDSWri:
   case AArch64::ADDSXrr:
   case AArch64::ADDSXri:
+  case AArch64::ADDSWrx:
+  case AArch64::ADDSXrx:
   case AArch64::SUBSWrr:
   case AArch64::SUBSWri:
+  case AArch64::SUBSWrx:
   case AArch64::SUBSXrr:
   case AArch64::SUBSXri:
+  case AArch64::SUBSXrx:
   case AArch64::ANDSWri:
   case AArch64::ANDSWrr:
   case AArch64::ANDSWrs:
@@ -1800,6 +1804,10 @@ static unsigned sForm(MachineInstr &Instr) {
     return AArch64::ADDSXrr;
   case AArch64::ADDXri:
     return AArch64::ADDSXri;
+  case AArch64::ADDWrx:
+    return AArch64::ADDSWrx;
+  case AArch64::ADDXrx:
+    return AArch64::ADDSXrx;
   case AArch64::ADCWr:
     return AArch64::ADCSWr;
   case AArch64::ADCXr:
@@ -1812,6 +1820,10 @@ static unsigned sForm(MachineInstr &Instr) {
     return AArch64::SUBSXrr;
   case AArch64::SUBXri:
     return AArch64::SUBSXri;
+  case AArch64::SUBWrx:
+    return AArch64::SUBSWrx;
+  case AArch64::SUBXrx:
+    return AArch64::SUBSXrx;
   case AArch64::SBCWr:
     return AArch64::SBCSWr;
   case AArch64::SBCXr:
diff --git a/llvm/test/CodeGen/AArch64/alias_mask.ll b/llvm/test/CodeGen/AArch64/alias_mask.ll
index 9b9c020016bab..c5d3677366480 100644
--- a/llvm/test/CodeGen/AArch64/alias_mask.ll
+++ b/llvm/test/CodeGen/AArch64/alias_mask.ll
@@ -393,70 +393,71 @@ entry:
 define <32 x i1> @whilewr_32_expand3(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_32_expand3:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x9, x1, x0
+; CHECK-NEXT:    sub x10, x1, x0
 ; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    add x10, x9, #3
-; CHECK-NEXT:    sub x11, x9, #61
-; CHECK-NEXT:    csel x10, x10, x9, mi
-; CHECK-NEXT:    subs x9, x9, #64
-; CHECK-NEXT:    csel x9, x11, x9, mi
-; CHECK-NEXT:    asr x10, x10, #2
-; CHECK-NEXT:    asr x9, x9, #2
+; CHECK-NEXT:    sub x9, x10, #61
+; CHECK-NEXT:    subs x11, x10, #64
+; CHECK-NEXT:    add x12, x10, #3
+; CHECK-NEXT:    csel x9, x9, x11, mi
+; CHECK-NEXT:    asr x11, x9, #2
 ; CHECK-NEXT:    mov z1.d, z0.d
 ; CHECK-NEXT:    mov z2.d, z0.d
 ; CHECK-NEXT:    mov z3.d, z0.d
+; CHECK-NEXT:    cmp x11, #1
 ; CHECK-NEXT:    mov z4.d, z0.d
 ; CHECK-NEXT:    mov z5.d, z0.d
+; CHECK-NEXT:    cset w9, lt
+; CHECK-NEXT:    cmp x10, #0
 ; CHECK-NEXT:    mov z6.d, z0.d
-; CHECK-NEXT:    dup v7.2d, x10
-; CHECK-NEXT:    dup v16.2d, x9
+; CHECK-NEXT:    csel x10, x12, x10, mi
+; CHECK-NEXT:    dup v7.2d, x11
 ; CHECK-NEXT:    add z1.d, z1.d, #12 // =0xc
+; CHECK-NEXT:    asr x10, x10, #2
 ; CHECK-NEXT:    add z2.d, z2.d, #10 // =0xa
-; CHECK-NEXT:    cmp x9, #1
 ; CHECK-NEXT:    add z3.d, z3.d, #8 // =0x8
 ; CHECK-NEXT:    add z4.d, z4.d, #6 // =0x6
 ; CHECK-NEXT:    add z5.d, z5.d, #4 // =0x4
 ; CHECK-NEXT:    add z6.d, z6.d, #2 // =0x2
+; CHECK-NEXT:    dup v16.2d, x10
 ; CHECK-NEXT:    cmhi v17.2d, v7.2d, v0.2d
-; CHECK-NEXT:    cmhi v18.2d, v16.2d, v0.2d
-; CHECK-NEXT:    add z0.d, z0.d, #14 // =0xe
 ; CHECK-NEXT:    cmhi v19.2d, v7.2d, v1.2d
 ; CHECK-NEXT:    cmhi v20.2d, v7.2d, v2.2d
 ; CHECK-NEXT:    cmhi v21.2d, v7.2d, v3.2d
+; CHECK-NEXT:    cmp x10, #1
 ; CHECK-NEXT:    cmhi v22.2d, v7.2d, v4.2d
-; CHECK-NEXT:    cmhi v23.2d, v7.2d, v5.2d
-; CHECK-NEXT:    cmhi v24.2d, v7.2d, v6.2d
+; CHECK-NEXT:    cset w10, lt
+; CHECK-NEXT:    cmhi v18.2d, v16.2d, v0.2d
+; CHECK-NEXT:    add z0.d, z0.d, #14 // =0xe
 ; CHECK-NEXT:    cmhi v1.2d, v16.2d, v1.2d
 ; CHECK-NEXT:    cmhi v2.2d, v16.2d, v2.2d
 ; CHECK-NEXT:    cmhi v3.2d, v16.2d, v3.2d
 ; CHECK-NEXT:    cmhi v4.2d, v16.2d, v4.2d
-; CHECK-NEXT:    cmhi v7.2d, v7.2d, v0.2d
-; CHECK-NEXT:    cmhi v5.2d, v16.2d, v5.2d
-; CHECK-NEXT:    cmhi v6.2d, v16.2d, v6.2d
-; CHECK-NEXT:    cset w9, lt
-; CHECK-NEXT:    cmhi v0.2d, v16.2d, v0.2d
-; CHECK-NEXT:    uzp1 v16.4s, v21.4s, v20.4s
-; CHECK-NEXT:    cmp x10, #1
-; CHECK-NEXT:    uzp1 v20.4s, v23.4s, v22.4s
-; CHECK-NEXT:    uzp1 v17.4s, v17.4s, v24.4s
-; CHECK-NEXT:    cset w10, lt
+; CHECK-NEXT:    cmhi v23.2d, v16.2d, v5.2d
+; CHECK-NEXT:    cmhi v24.2d, v16.2d, v6.2d
+; CHECK-NEXT:    cmhi v5.2d, v7.2d, v5.2d
+; CHECK-NEXT:    cmhi v16.2d, v16.2d, v0.2d
+; CHECK-NEXT:    cmhi v6.2d, v7.2d, v6.2d
+; CHECK-NEXT:    cmhi v0.2d, v7.2d, v0.2d
+; CHECK-NEXT:    uzp1 v7.4s, v21.4s, v20.4s
 ; CHECK-NEXT:    uzp1 v2.4s, v3.4s, v2.4s
-; CHECK-NEXT:    uzp1 v3.4s, v19.4s, v7.4s
-; CHECK-NEXT:    uzp1 v4.4s, v5.4s, v4.4s
-; CHECK-NEXT:    uzp1 v5.4s, v18.4s, v6.4s
-; CHECK-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT:    uzp1 v1.8h, v17.8h, v20.8h
-; CHECK-NEXT:    uzp1 v3.8h, v16.8h, v3.8h
-; CHECK-NEXT:    uzp1 v4.8h, v5.8h, v4.8h
-; CHECK-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-NEXT:    dup v2.16b, w10
-; CHECK-NEXT:    uzp1 v1.16b, v1.16b, v3.16b
-; CHECK-NEXT:    dup v3.16b, w9
+; CHECK-NEXT:    uzp1 v3.4s, v23.4s, v4.4s
+; CHECK-NEXT:    uzp1 v4.4s, v18.4s, v24.4s
+; CHECK-NEXT:    uzp1 v5.4s, v5.4s, v22.4s
+; CHECK-NEXT:    uzp1 v1.4s, v1.4s, v16.4s
+; CHECK-NEXT:    uzp1 v6.4s, v17.4s, v6.4s
+; CHECK-NEXT:    uzp1 v0.4s, v19.4s, v0.4s
+; CHECK-NEXT:    uzp1 v3.8h, v4.8h, v3.8h
+; CHECK-NEXT:    uzp1 v1.8h, v2.8h, v1.8h
+; CHECK-NEXT:    uzp1 v2.8h, v6.8h, v5.8h
+; CHECK-NEXT:    uzp1 v0.8h, v7.8h, v0.8h
+; CHECK-NEXT:    uzp1 v1.16b, v3.16b, v1.16b
+; CHECK-NEXT:    uzp1 v0.16b, v2.16b, v0.16b
+; CHECK-NEXT:    dup v3.16b, w10
+; CHECK-NEXT:    dup v2.16b, w9
 ; CHECK-NEXT:    adrp x9, .LCPI14_0
-; CHECK-NEXT:    uzp1 v0.16b, v4.16b, v0.16b
-; CHECK-NEXT:    orr v1.16b, v1.16b, v2.16b
+; CHECK-NEXT:    orr v1.16b, v1.16b, v3.16b
+; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI14_0]
-; CHECK-NEXT:    orr v0.16b, v0.16b, v3.16b
 ; CHECK-NEXT:    shl v1.16b, v1.16b, #7
 ; CHECK-NEXT:    shl v0.16b, v0.16b, #7
 ; CHECK-NEXT:    cmlt v1.16b, v1.16b, #0
@@ -586,70 +587,71 @@ entry:
 define <32 x i1> @whilewr_64_expand4(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_64_expand4:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x9, x1, x0
+; CHECK-NEXT:    sub x10, x1, x0
 ; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    add x10, x9, #7
-; CHECK-NEXT:    sub x11, x9, #121
-; CHECK-NEXT:    csel x10, x10, x9, mi
-; CHECK-NEXT:    subs x9, x9, #128
-; CHECK-NEXT:    csel x9, x11, x9, mi
-; CHECK-NEXT:    asr x10, x10, #3
-; CHECK-NEXT:    asr x9, x9, #3
+; CHECK-NEXT:    sub x9, x10, #121
+; CHECK-NEXT:    subs x11, x10, #128
+; CHECK-NEXT:    add x12, x10, #7
+; CHECK-NEXT:    csel x9, x9, x11, mi
+; CHECK-NEXT:    asr x11, x9, #3
 ; CHECK-NEXT:    mov z1.d, z0.d
 ; CHECK-NEXT:    mov z2.d, z0.d
 ; CHECK-NEXT:    mov z3.d, z0.d
+; CHECK-NEXT:    cmp x11, #1
 ; CHECK-NEXT:    mov z4.d, z0.d
 ; CHECK-NEXT:    mov z5.d, z0.d
+; CHECK-NEXT:    cset w9, lt
+; CHECK-NEXT:    cmp x10, #0
 ; CHECK-NEXT:    mov z6.d, z0.d
-; CHECK-NEXT:    dup v7.2d, x10
-; CHECK-NEXT:    dup v16.2d, x9
+; CHECK-NEXT:    csel x10, x12, x10, mi
+; CHECK-NEXT:    dup v7.2d, x11
 ; CHECK-NEXT:    add z1.d, z1.d, #12 // =0xc
+; CHECK-NEXT:    asr x10, x10, #3
 ; CHECK-NEXT:    add z2.d, z2.d, #10 // =0xa
-; CHECK-NEXT:    cmp x9, #1
 ; CHECK-NEXT:    add z3.d, z3.d, #8 // =0x8
 ; CHECK-NEXT:    add z4.d, z4.d, #6 // =0x6
 ; CHECK-NEXT:    add z5.d, z5.d, #4 // =0x4
 ; CHECK-NEXT:    add z6.d, z6.d, #2 // =0x2
+; CHECK-NEXT:    dup v16.2d, x10
 ; CHECK-NEXT:    cmhi v17.2d, v7.2d, v0.2d
-; CHECK-NEXT:    cmhi v18.2d, v16.2d, v0.2d
-; CHECK-NEXT:    add z0.d, z0.d, #14 // =0xe
 ; CHECK-NEXT:    cmhi v19.2d, v7.2d, v1.2d
 ; CHECK-NEXT:    cmhi v20.2d, v7.2d, v2.2d
 ; CHECK-NEXT:    cmhi v21.2d, v7.2d, v3.2d
+; CHECK-NEXT:    cmp x10, #1
 ; CHECK-NEXT:    cmhi v22.2d, v7.2d, v4.2d
-; CHECK-NEXT:    cmhi v23.2d, v7.2d, v5.2d
-; CHECK-NEXT:    cmhi v24.2d, v7.2d, v6.2d
+; CHECK-NEXT:    cset w10, lt
+; CHECK-NEXT:    cmhi v18.2d, v16.2d, v0.2d
+; CHECK-NEXT:    add z0.d, z0.d, #14 // =0xe
 ; CHECK-NEXT:    cmhi v1.2d, v16.2d, v1.2d
 ; CHECK-NEXT:    cmhi v2.2d, v16.2d, v2.2d
 ; CHECK-NEXT:    cmhi v3.2d, v16.2d, v3.2d
 ; CHECK-NEXT:    cmhi v4.2d, v16.2d, v4.2d
-; CHECK-NEXT:    cmhi v7.2d, v7.2d, v0.2d
-; CHECK-NEXT:    cmhi v5.2d, v16.2d, v5.2d
-; CHECK-NEXT:    cmhi v6.2d, v16.2d, v6.2d
-; CHECK-NEXT:    cset w9, lt
-; CHECK-NEXT:    cmhi v0.2d, v16.2d, v0.2d
-; CHECK-NEXT:    uzp1 v16.4s, v21.4s, v20.4s
-; CHECK-NEXT:    cmp x10, #1
-; CHECK-NEXT:    uzp1 v20.4s, v23.4s, v22.4s
-; CHECK-NEXT:    uzp1 v17.4s, v17.4s, v24.4s
-; CHECK-NEXT:    cset w10, lt
+; CHECK-NEXT:    cmhi v23.2d, v16.2d, v5.2d
+; CHECK-NEXT:    cmhi v24.2d, v16.2d, v6.2d
+; CHECK-NEXT:    cmhi v5.2d, v7.2d, v5.2d
+; CHECK-NEXT:    cmhi v16.2d, v16.2d, v0.2d
+; CHECK-NEXT:    cmhi v6.2d, v7.2d, v6.2d
+; CHECK-NEXT:    cmhi v0.2d, v7.2d, v0.2d
+; CHECK-NEXT:    uzp1 v7.4s, v21.4s, v20.4s
 ; CHECK-NEXT:    uzp1 v2.4s, v3.4s, v2.4s
-; CHECK-NEXT:    uzp1 v3.4s, v19.4s, v7.4s
-; CHECK-NEXT:    uzp1 v4.4s, v5.4s, v4.4s
-; CHECK-NEXT:    uzp1 v5.4s, v18.4s, v6.4s
-; CHECK-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT:    uzp1 v1.8h, v17.8h, v20.8h
-; CHECK-NEXT:    uzp1 v3.8h, v16.8h, v3.8h
-; CHECK-NEXT:    uzp1 v4.8h, v5.8h, v4.8h
-; CHECK-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-NEXT:    dup v2.16b, w10
-; CHECK-NEXT:    uzp1 v1.16b, v1.16b, v3.16b
-; CHECK-NEXT:    dup v3.16b, w9
+; CHECK-NEXT:    uzp1 v3.4s, v23.4s, v4.4s
+; CHECK-NEXT:    uzp1 v4.4s, v18.4s, v24.4s
+; CHECK-NEXT:    uzp1 v5.4s, v5.4s, v22.4s
+; CHECK-NEXT:    uzp1 v1.4s, v1.4s, v16.4s
+; CHECK-NEXT:    uzp1 v6.4s, v17.4s, v6.4s
+; CHECK-NEXT:    uzp1 v0.4s, v19.4s, v0.4s
+; CHECK-NEXT:    uzp1 v3.8h, v4.8h, v3.8h
+; CHECK-NEXT:    uzp1 v1.8h, v2.8h, v1.8h
+; CHECK-NEXT:    uzp1 v2.8h, v6.8h, v5.8h
+; CHECK-NEXT:    uzp1 v0.8h, v7.8h, v0.8h
+; CHECK-NEXT:    uzp1 v1.16b, v3.16b, v1.16b
+; CHECK-NEXT:    uzp1 v0.16b, v2.16b, v0.16b
+; CHECK-NEXT:    dup v3.16b, w10
+; CHECK-NEXT:    dup v2.16b, w9
 ; CHECK-NEXT:    adrp x9, .LCPI18_0
-; CHECK-NEXT:    uzp1 v0.16b, v4.16b, v0.16b
-; CHECK-NEXT:    orr v1.16b, v1.16b, v2.16b
+; CHECK-NEXT:    orr v1.16b, v1.16b, v3.16b
+; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI18_0]
-; CHECK-NEXT:    orr v0.16b, v0.16b, v3.16b
 ; CHECK-NEXT:    shl v1.16b, v1.16b, #7
 ; CHECK-NEXT:    shl v0.16b, v0.16b, #7
 ; CHECK-NEXT:    cmlt v1.16b, v1.16b, #0
@@ -790,11 +792,10 @@ entry:
 define <1 x i1> @whilewr_8_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_8_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #0
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 1)
@@ -804,11 +805,10 @@ entry:
 define <1 x i1> @whilewr_16_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_16_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #1
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 2)
@@ -818,11 +818,10 @@ entry:
 define <1 x i1> @whilewr_32_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_32_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #3
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 4)
@@ -832,11 +831,10 @@ entry:
 define <1 x i1> @whilewr_64_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilewr_64_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #7
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 8)
@@ -846,11 +844,10 @@ entry:
 define <1 x i1> @whilerw_8_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilerw_8_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #0
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 1)
@@ -860,11 +857,10 @@ entry:
 define <1 x i1> @whilerw_16_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilerw_16_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #1
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 2)
@@ -874,11 +870,10 @@ entry:
 define <1 x i1> @whilerw_32_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilerw_32_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #3
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 4)
@@ -888,11 +883,10 @@ entry:
 define <1 x i1> @whilerw_64_scalarize(ptr %a, ptr %b) {
 ; CHECK-LABEL: whilerw_64_scalarize:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    subs x8, x1, x0
+; CHECK-NEXT:    sub x8, x1, x0
 ; CHECK-NEXT:    cmp x8, #7
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    cmp x1, x0
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-NEXT:    ccmp x8, #0, #4, le
+; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 8)
diff --git a/llvm/test/CodeGen/AArch64/csel-subs-dag-combine.ll b/llvm/test/CodeGen/AArch64/csel-subs-dag-combine.ll
deleted file mode 100644
index 5036be9c45e69..0000000000000
--- a/llvm/test/CodeGen/AArch64/csel-subs-dag-combine.ll
+++ /dev/null
@@ -1,112 +0,0 @@
-; RUN: llc -debug-only=isel -o /dev/null < %s 2>&1 | FileCheck %s
-
-; REQUIRES: asserts
-
-; These tests ensure that we don't combine
-;   CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y)
-; if the flags set by SUBS(SUB(x,y), 0) have more than one use.
-;
-; This restriction exists because combining SUBS(SUB(x,y), 0) -> SUBS(x,y) is
-; only valid if there are no users of the overflow flags (C/V) generated by the
-; SUBS. Currently, we only check the flags used by the CSEL, and therefore we
-; conservatively reject cases where the SUBS's flags have other uses.
-
-target triple = "aarch64-unknown-linux-gnu"
-
-; CHECK-LABEL: Legalized selection DAG: %bb.0 'combine_subs:'
-; CHECK-NEXT: SelectionDAG has 13 nodes:
-; CHECK-NEXT:   t0: ch,glue = EntryToken
-; CHECK-NEXT:   t2: i32,ch = CopyFromReg t0, Register:i32 %0
-; CHECK-NEXT:   t4: i32,ch = CopyFromReg t0, Register:i32 %1
-; CHECK-NEXT:         t5: i32 = sub t2, t4
-; CHECK-NEXT:       t14: i32,i32 = AArch64ISD::SUBS t5, Constant:i32<0>
-; CHECK-NEXT:     t16: i32 = AArch64ISD::CSEL t2, t4, Constant:i32<1>, t14:1
-; CHECK-NEXT:   t11: ch,glue = CopyToReg t0, Register:i32 $w0, t16
-; CHECK-NEXT:   t12: ch = AArch64ISD::RET_GLUE t11, Register:i32 $w0, t11:1
-
-; CHECK-LABEL: Optimized legalized selection DAG: %bb.0 'combine_subs:'
-; CHECK-NEXT: SelectionDAG has 11 nodes:
-; CHECK-NEXT:   t0: ch,glue = EntryToken
-; CHECK-NEXT:   t2: i32,ch = CopyFromReg t0, Register:i32 %0
-; CHECK-NEXT:   t4: i32,ch = CopyFromReg t0, Register:i32 %1
-; CHECK-NEXT:       t18: i32,i32 = AArch64ISD::SUBS t2, t4
-; CHECK-NEXT:     t16: i32 = AArch64ISD::CSEL t2, t4, Constant:i32<1>, t18:1
-; CHECK-NEXT:   t11: ch,glue = CopyToReg t0, Register:i32 $w0, t16
-; CHECK-NEXT:   t12: ch = AArch64ISD::RET_GLUE t11, Register:i32 $w0, t11:1
-
-define i32 @combine_subs(i32 %a, i32 %b) {
-  %sub = sub i32 %a, %b
-  %cc = icmp ne i32 %sub, 0
-  %sel = select i1 %cc, i32 %a, i32 %b
-  ret i32 %sel
-}
-
-; CHECK-LABEL: Legalized selection DAG: %bb.0 'combine_subs_multiple_sub_uses:'
-; CHECK-NEXT: SelectionDAG has 14 nodes:
-; CHECK-NEXT:   t0: ch,glue = EntryToken
-; CHECK-NEXT:   t2: i32,ch = CopyFromReg t0, Register:i32 %0
-; CHECK-NEXT:   t4: i32,ch = CopyFromReg t0, Register:i32 %1
-; CHECK-NEXT:   t5: i32 = sub t2, t4
-; CHECK-NEXT:         t15: i32,i32 = AArch64ISD::SUBS t5, Constant:i32<0>
-; CHECK-NEXT:       t17: i32 = AArch64ISD::CSEL t2, t4, Constant:i32<1>, t15:1
-; CHECK-NEXT:     t10: i32 = add t17, t5
-; CHECK-NEXT:   t12: ch,glue = CopyToReg t0, Register:i32 $w0, t10
-; CHECK-NEXT:   t13: ch = AArch64ISD::RET_GLUE t12, Register:i32 $w0, t12:1
-
-; CHECK-LABEL: Optimized legalized selection DAG: %bb.0 'combine_subs_multiple_sub_uses:'
-; CHECK-NEXT: SelectionDAG has 12 nodes:
-; CHECK-NEXT:   t0: ch,glue = EntryToken
-; CHECK-NEXT:   t2: i32,ch = CopyFromReg t0, Register:i32 %0
-; CHECK-NEXT:   t4: i32,ch = CopyFromReg t0, Register:i32 %1
-; CHECK-NEXT:       t17: i32 = AArch64ISD::CSEL t2, t4, Constant:i32<1>, t19:1
-; CHECK-NEXT:     t10: i32 = add t17, t19
-; CHECK-NEXT:   t12: ch,glue = CopyToReg t0, Register:i32 $w0, t10
-; CHECK-NEXT:   t19: i32,i32 = AArch64ISD::SUBS t2, t4
-; CHECK-NEXT:   t13: ch = AArch64ISD::RET_GLUE t12, Register:i32 $w0, t12:1
-
-define i32 @combine_subs_multiple_sub_uses(i32 %a, i32 %b) {
-  %sub = sub i32 %a, %b
-  %cc = icmp ne i32 %sub, 0
-  %sel = select i1 %cc, i32 %a, i32 %b
-  %add = add i32 %sel, %sub
-  ret i32 %add
-}
-
-; CHECK-LABEL: Legalized selection DAG: %bb.0 'do_not_combine_subs_multiple_flag_uses:'
-; CHECK-NEXT: SelectionDAG has 19 nodes:
-; CHECK-NEXT:   t0: ch,glue = EntryToken
-; CHECK-NEXT:   t2: i32,ch = CopyFromReg t0, Register:i32 %0
-; CHECK-NEXT:   t4: i32,c...
[truncated]

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SiliconA-Z commented Nov 11, 2025

@davemgreen @MacDue Thoughts?

nasherm
nasherm approved these changes Nov 12, 2025
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Thanks for this. LGTM

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SiliconA-Z commented Nov 12, 2025

Thank you. Can you please merge @nasherm

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SiliconA-Z commented Nov 12, 2025

@RKSimon

@RKSimon RKSimon enabled auto-merge (squash) November 13, 2025 13:06
@RKSimon RKSimon merged commit e5baf07 into llvm:main Nov 13, 2025
9 of 10 checks passed
@SiliconA-Z SiliconA-Z deleted the ede-part-3 branch November 13, 2025 14:39
@juliannagele
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juliannagele commented Nov 14, 2025

This seems to have broken llvm/test/CodeGen/AArch64/alias_mask.ll on one of the green dragon bots: https://ci.swift.org/job/llvm.org/job/clang-stage1-cmake-RA-expensive/5703/testReport/junit/LLVM/CodeGen_AArch64/alias_mask_ll/
Could you have a look?

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SiliconA-Z commented Nov 14, 2025

This seems to have broken llvm/test/CodeGen/AArch64/alias_mask.ll on one of the green dragon bots: https://ci.swift.org/job/llvm.org/job/clang-stage1-cmake-RA-expensive/5703/testReport/junit/LLVM/CodeGen_AArch64/alias_mask_ll/ Could you have a look?

Okay...

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SiliconA-Z commented Nov 14, 2025

I don't see how this error happens on my end. It is not.

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SiliconA-Z commented Nov 14, 2025

Let me double check.

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SiliconA-Z commented Nov 14, 2025

This seems to have broken llvm/test/CodeGen/AArch64/alias_mask.ll on one of the green dragon bots: https://ci.swift.org/job/llvm.org/job/clang-stage1-cmake-RA-expensive/5703/testReport/junit/LLVM/CodeGen_AArch64/alias_mask_ll/ Could you have a look?

Cannot repro... But hold on...

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SiliconA-Z commented Nov 14, 2025

Yeah if this isn't working, I can't see it on my machine or the other buildbots we have

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RKSimon commented Nov 14, 2025

Is that a EXPENSIVE_CHECKS build?

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SiliconA-Z commented Nov 14, 2025

Yeah it seems to be.

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juliannagele commented Nov 15, 2025

It is yes, this fails on my local machine:

$ cmake -G Ninja \
  -DCMAKE_BUILD_TYPE=Release \
  -DLLVM_ENABLE_PROJECTS="clang;llvm" \
  -DLLVM_ENABLE_ASSERTIONS=On \
  -DLLVM_ENABLE_EXPENSIVE_CHECKS=On \
  -DLLVM_TARGETS_TO_BUILD="AArch64" \
  path/to/llvm-project/llvm
$ ninja check-llvm-codegen-aarch64
...
FAIL: LLVM :: CodeGen/AArch64/alias_mask.ll (1 of 3782)
******************** TEST 'LLVM :: CodeGen/AArch64/alias_mask.ll' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/Users/jnagele/llvm-project/build/Release/bin/llc -mtriple=aarch64 -mattr=+sve2 /Users/jnagele/llvm-project/llvm/test/CodeGen/AArch64/alias_mask.ll -o - | /Users/jnagele/llvm-project/build/Release/bin/FileCheck /Users/jnagele/llvm-project/llvm/test/CodeGen/AArch64/alias_mask.ll
# executed command: /Users/jnagele/llvm-project/build/Release/bin/llc -mtriple=aarch64 -mattr=+sve2 /Users/jnagele/llvm-project/llvm/test/CodeGen/AArch64/alias_mask.ll -o -
# .---command stderr------------
# |
# | # After Instruction Selection
# | # Machine code for function whilewr_8_scalarize: IsSSA, TracksLiveness
# | Function Live Ins: $x0 in %0, $x1 in %1
# |
# | bb.0.entry:
# |   liveins: $x0, $x1
# |   %1:gpr64 = COPY $x1
# |   %0:gpr64 = COPY $x0
# |   %2:gpr64common = SUBSXrr %1:gpr64, %0:gpr64, implicit-def dead $nzcv
# |   %3:gpr64 = SUBSXri %2:gpr64common, 0, 0, implicit-def $nzcv
# |   CCMPXr %2:gpr64common, 0, 4, 13, implicit-def $nzcv, implicit $nzcv
# |   %4:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
# |   $w0 = COPY %4:gpr32
# |   RET_ReallyLR implicit $w0
# |
# | # End machine code for function whilewr_8_scalarize.
# |
# | *** Bad machine code: Expected a register operand. ***
# | - function:    whilewr_8_scalarize
# | - basic block: %bb.0 entry (0x109034d18)
# | - instruction: CCMPXr %2:gpr64common, 0, 4, 13, implicit-def $nzcv, implicit $nzcv
# | - operand 1:   0
# | LLVM ERROR: Found 1 machine code errors.
...

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SiliconA-Z commented Nov 15, 2025

Fix is here: #168221 (comment)

@SiliconA-Z SiliconA-Z mentioned this pull request Nov 15, 2025
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