PPC: Replace PointerLikeRegClass with RegClassByHwMode

[arsenm]

No description provided.

[arsenm]

• PPC: Replace PointerLikeRegClass with RegClassByHwMode #158777 👈 (View in Graphite)
• CodeGen: Add RegisterClass by HwMode #158269 : 4 other dependent PRs (#158271 , #158272 , #158273 and 1 other)
• main

This stack of pull requests is managed by Graphite. Learn more about stacking.

[llvmbot]

@llvm/pr-subscribers-backend-powerpc
@llvm/pr-subscribers-llvm-mc
@llvm/pr-subscribers-backend-systemz

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/158777.diff

4 Files Affected:

• (modified) llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (-3)
• (modified) llvm/lib/Target/PowerPC/PPC.td (+6)
• (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+9-19)
• (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.td (+8-2)

diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 47586c417cfe3..70e619cc22b19 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
   return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
 }
 
-#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
-#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
-
 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 386d0f65d1ed1..d491e88b66ad8 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
 def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
 def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
 
+//===----------------------------------------------------------------------===//
+// HwModes
+//===----------------------------------------------------------------------===//
+
+defvar PPC32 = DefaultMode;
+def PPC64 : HwMode<[In64BitMode]>;
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index db066bc4b7bdd..55e38bcf4afc9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
   assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
   assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
 
-  const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx];
-
   // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
   // register (which might also be specified as a pointer class kind).
-  if (UseInfo->isLookupPtrRegClass()) {
-    if (UseInfo->RegClass /* Kind */ != 1)
-      return false;
-  } else {
-    if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
-        UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
-      return false;
-  }
+
+  const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx];
+  int16_t RegClass = getOpRegClassID(UseInfo);
+  if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID &&
+      UseInfo.RegClass != PPC::G8RC_NOX0RegClassID)
+    return false;
 
   // Make sure this is not tied to an output register (or otherwise
   // constrained). This is true for ST?UX registers, for example, which
   // are tied to their output registers.
-  if (UseInfo->Constraints != 0)
+  if (UseInfo.Constraints != 0)
     return false;
 
-  MCRegister ZeroReg;
-  if (UseInfo->isLookupPtrRegClass()) {
-    bool isPPC64 = Subtarget.isPPC64();
-    ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
-  } else {
-    ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
-              PPC::ZERO8 : PPC::ZERO;
-  }
+  MCRegister ZeroReg =
+      RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO;
 
   LLVM_DEBUG(dbgs() << "Folded immediate zero for: ");
   LLVM_DEBUG(UseMI.dump());
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8b690b7b833b3..adda91786d19c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -868,7 +868,11 @@ def crbitm: Operand<i8> {
 def PPCRegGxRCNoR0Operand : AsmOperandClass {
   let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand<iPTR>,
+  RegClassByHwMode<
+    [PPC32, PPC64],
+    [GPRC_NOR0, G8RC_NOX0]> {
   let ParserMatchClass = PPCRegGxRCNoR0Operand;
 }
 
@@ -902,7 +906,9 @@ def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
 def PPCRegGxRCOperand : AsmOperandClass {
   let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
+def ptr_rc_idx : Operand<iPTR>,
+  RegClassByHwMode<[PPC32, PPC64],
+                   [GPRC, G8RC]> {
   let ParserMatchClass = PPCRegGxRCOperand;
 }
 

[s-barannikov]

Maybe swap the names of RegClassByHwMode / RegisterOperand to reduce diff?

[s-barannikov]

LGTM
Is there a reason to not implement the renaming suggestion? (Like it would require renaming methods in C++ files or make the naming inconsistent.)

[arsenm]

Most of the operands seem capitalized

[s-barannikov]

They seem all lowercase to me 🤷‍♂️

spoiler

$ grep -E ": (Register)?Operand" llvm/lib/Target/PowerPC/*.td | cut -d ':' -f 2,3

def s16imm64 : Operand<i64> {
def u16imm64 : Operand<i64> {
def s17imm64 : Operand<i64> {
def tocentry : Operand<iPTR> {
def tlsreg : Operand<i64> {
def tlsgd : Operand<i64> {}
def tlscall : Operand<i64> {
def tocentry32 : Operand<iPTR> {
def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
def gprc : RegisterOperand<GPRC> {
def g8rc : RegisterOperand<G8RC> {
def g8prc : RegisterOperand<G8pRC> {
def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
def f8rc : RegisterOperand<F8RC> {
def f4rc : RegisterOperand<F4RC> {
def fpairrc : RegisterOperand<FpRC> {
def vrrc : RegisterOperand<VRRC> {
def vfrc : RegisterOperand<VFRC> {
def crbitrc : RegisterOperand<CRBITRC> {
def crrc : RegisterOperand<CRRC> {
def sperc : RegisterOperand<SPERC> {
def spe4rc : RegisterOperand<GPRC> {
def u1imm   : Operand<i32> {
def u2imm   : Operand<i32> {
def atimm   : Operand<i32> {
def u3imm   : Operand<i32> {
def u4imm   : Operand<i32> {
def s5imm   : Operand<i32> {
def u5imm   : Operand<i32> {
def u6imm   : Operand<i32> {
def u7imm   : Operand<i32> {
def u8imm   : Operand<i32> {
def u10imm  : Operand<i32> {
def u12imm  : Operand<i32> {
def s16imm  : Operand<i32> {
def u16imm  : Operand<i32> {
def s17imm  : Operand<i32> {
def s34imm : Operand<i64> {
def s34imm_pcrel : Operand<i64> {
def immZero : Operand<i32> {
def directbrtarget : Operand<OtherVT> {
def absdirectbrtarget : Operand<OtherVT> {
def condbrtarget : Operand<OtherVT> {
def abscondbrtarget : Operand<OtherVT> {
def calltarget : Operand<iPTR> {
def abscalltarget : Operand<iPTR> {
def crbitm: Operand<i8> {
def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
def dispRI34 : Operand<iPTR> {
def dispRI34_pcrel : Operand<iPTR> {
def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value.
def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
def dispRI : Operand<iPTR> {
def dispRIX : Operand<iPTR> {
def dispRIHash : Operand<iPTR> {
def dispRIX16 : Operand<iPTR> {
def dispSPE8 : Operand<iPTR> {
def dispSPE4 : Operand<iPTR> {
def dispSPE2 : Operand<iPTR> {
def memri : Operand<iPTR> {
def memrr : Operand<iPTR> {
def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
def memrihash : Operand<iPTR> {
def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16
def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
def memr : Operand<iPTR> {
def tlsreg32 : Operand<i32> {
def tlsgd32 : Operand<i32> {}
def tlscall32 : Operand<i32> {
def pred : Operand<OtherVT> {
def vsrc : RegisterOperand<VSRC> {
def vsfrc : RegisterOperand<VSFRC> {
def vssrc : RegisterOperand<VSSRC> {
def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> {
def vsrprc : RegisterOperand<VSRpRC> {
def vsrpevenrc : RegisterOperand<VSRpRC> {
def acc : RegisterOperand<ACCRC> {
def uacc : RegisterOperand<UACCRC> {
def dmrrow : RegisterOperand<DMRROWRC> {
def dmrrowp : RegisterOperand<DMRROWpRC> {
def wacc : RegisterOperand<WACCRC> {
def wacc_hi : RegisterOperand<WACC_HIRC> {
def dmr : RegisterOperand<DMRRC> {
def dmrp : RegisterOperand<DMRpRC> {

[arsenm]

They seem all lowercase to me 🤷‍♂️

spoiler

For some reason I looked at the AsmOperandClass as examples and those are uppercase