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[RISCV][NFC] Combine RISCVOptWInstrs::stripWSuffixes and appendWSuffixes into canonicalizeWSuffixes #149710

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Merged
merged 1 commit into from
Jul 21, 2025
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[RISCV][NFC] Combine RISCVOptWInstrs::stripWSuffixes and appendWSuffixes into canonicalizeWSuffixes #149710

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94 changes: 41 additions & 53 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -69,10 +69,9 @@ class RISCVOptWInstrs : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
bool stripWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
bool appendWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
bool canonicalizeWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI);

void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
Expand Down Expand Up @@ -723,51 +722,38 @@ bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
return MadeChange;
}

bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
// Strips or adds W suffixes to eligible instructions depending on the
// subtarget preferences.
bool RISCVOptWInstrs::canonicalizeWSuffixes(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
bool ShouldStripW = !(DisableStripWSuffix || ST.preferWInst());
bool ShouldPreferW = ST.preferWInst();
bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
unsigned Opc;
// clang-format off
switch (MI.getOpcode()) {
default:
continue;
case RISCV::ADDW: Opc = RISCV::ADD; break;
case RISCV::ADDIW: Opc = RISCV::ADDI; break;
case RISCV::MULW: Opc = RISCV::MUL; break;
case RISCV::SLLIW: Opc = RISCV::SLLI; break;
case RISCV::SUBW: Opc = RISCV::SUB; break;
}
// clang-format on

if (hasAllWUsers(MI, ST, MRI)) {
LLVM_DEBUG(dbgs() << "Replacing " << MI);
MI.setDesc(TII.get(Opc));
LLVM_DEBUG(dbgs() << " with " << MI);
++NumTransformedToNonWInstrs;
MadeChange = true;
}
}
}

return MadeChange;
}

bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
unsigned WOpc;
// TODO: Add more?
std::optional<unsigned> WOpc;
std::optional<unsigned> NonWOpc;
switch (MI.getOpcode()) {
default:
continue;
case RISCV::ADDW:
NonWOpc = RISCV::ADD;
break;
case RISCV::ADDIW:
NonWOpc = RISCV::ADDI;
break;
case RISCV::MULW:
NonWOpc = RISCV::MUL;
break;
case RISCV::SLLIW:
NonWOpc = RISCV::SLLI;
break;
case RISCV::SUBW:
NonWOpc = RISCV::SUB;
break;
case RISCV::ADD:
WOpc = RISCV::ADDW;
break;
Expand All @@ -781,7 +767,7 @@ bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
WOpc = RISCV::MULW;
break;
case RISCV::SLLI:
// SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
// SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits.
if (MI.getOperand(2).getImm() >= 32)
continue;
WOpc = RISCV::SLLIW;
Expand All @@ -792,19 +778,27 @@ bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
break;
}

if (hasAllWUsers(MI, ST, MRI)) {
if (ShouldStripW && NonWOpc.has_value() && hasAllWUsers(MI, ST, MRI)) {
LLVM_DEBUG(dbgs() << "Replacing " << MI);
MI.setDesc(TII.get(WOpc));
MI.setDesc(TII.get(NonWOpc.value()));
LLVM_DEBUG(dbgs() << " with " << MI);
++NumTransformedToNonWInstrs;
MadeChange = true;
continue;
}
if (ShouldPreferW && WOpc.has_value() && hasAllWUsers(MI, ST, MRI)) {
LLVM_DEBUG(dbgs() << "Replacing " << MI);
MI.setDesc(TII.get(WOpc.value()));
MI.clearFlag(MachineInstr::MIFlag::NoSWrap);
MI.clearFlag(MachineInstr::MIFlag::NoUWrap);
MI.clearFlag(MachineInstr::MIFlag::IsExact);
LLVM_DEBUG(dbgs() << " with " << MI);
++NumTransformedToWInstrs;
MadeChange = true;
continue;
}
}
}

return MadeChange;
}

Expand All @@ -821,12 +815,6 @@ bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {

bool MadeChange = false;
MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);

if (!(DisableStripWSuffix || ST.preferWInst()))
MadeChange |= stripWSuffixes(MF, TII, ST, MRI);

if (ST.preferWInst())
MadeChange |= appendWSuffixes(MF, TII, ST, MRI);

MadeChange |= canonicalizeWSuffixes(MF, TII, ST, MRI);
return MadeChange;
}
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