Updated README

'

CPUKit/PLD/IRCTRL/IRCTRL.PLD → CPUKit_InDev/PLD/IRCTRL/IRCTRL.PLD

@@ -640,7 +640,6 @@ IR2_LATCH.d = !( ( SM_F2 ) );
 JMPINST.d = !(INST_ALL_JMP);
 HALT.d = !( INST_HALT );     
 D2A_OE.d = !(INST_RET_2);
-
 A2D_OE.d = 'b'1;
 
 /*

README.md

@@ -0,0 +1,85 @@
+# Kartana9
+A simple 16-bit CPU implemented completely in a collection of ATF15XX CPLDs.
+
+This is an implemenation of a simple 16-bit CPU design using ATF5XX CPLDs on a single  4-layer PCBs.   
+
+The goal was to pick a simple instruction set that would allow for simple assembly language programs.  With a 16 bit address bus capable of addressig 64K of memory it was important for the ISA to support relative offsets and fully relocatable code.  While the first iteration does not have a multiply or divide instruction, some features in the shifting mechanism have been enhanced to make it easy to implment.
+
+![](/images/IMG_6812.jpeg)
+
+## Instruction Set Architecture
+
+The instruction set is a RISC-like load-store design with support for 8 general purpose 16 bit registers as well as two special purpose registers (Stack Pointer and Program Counter)   The internal data path is 16-bits wide, as are the registers and the external data path.  Access to external memory can be either 8 or 16 bits wide with automatic byte shifting to support loads 8 bit values from any address. 
+
+Signed and Unsigned comparisons are supported, as are with and without carry/borrow math operations.  
+
+Stack operations are also supported.
+
+Call/Return functionality is support with return address storage on the stack.
+
+Instructions fall in to 2 size catagories:  
+  - Single Word Instructions (16 bits in width)
+  - Double Word Instructions (32 bits in width)
+
+Instruction Execution time also falls into two catagories:
+  - Single Cycle execution (most of the instructions)
+  - Two Cycle execution 
+
+The fastest instructions have 1 fetch cycle and 1 execution cycle, while the slowest instruction has 2 fetch cycles and 2 executions cycles. I would expect average throughput to be ~2.2 cycles/instruction.
+
+Instruction Set:
+
+![](/InstructionsA.jpg)
+![](/InstructionsB.jpg)
+
+Most ALU operations are 3 operand, and there are no restrictions on those operands.  Each can be any of the 8 general purpose registers, and they do not need to be unique.
+
+As an example:
+
+`XOR R1,R1,R1`
+
+would clear the R1 register, since and XOR against the same value results in zero.
+
+The ALU operations ADD and SUB have variants that use the carry flag, and a side effect was added to the OR/XOR/AND/NOT operation to clear the carry flag.   You can use an instruction like OR R1,R1,R1 to make no changes except the CF clear.
+
+Load and Store operations use either an immediate address, a relative immediate address,  or an address in a register.  Both Load and Store have BYTE and WORD varients.
+
+The shift instructions include the standard logical right and left as well as arithmetic right. There is an additional shift left with CARRY FILL, an instruction that can be used in some division algorythms.
+
+The JUMP operations is to an address in a register, a direct immeditate addresss, or a reltive address (for relocatable code).  CALL (subroutine) operations also support register, a direct immeditate addresss, or a reltive address.
+
+All decode and operation logic is direct sequential logic implemented inside the CPLDs with no microcode.  
+
+## Physcial Implementation
+
+The CPU is implemented on a 4-layer PCBs using ATF1508 CPLDs.  
+
+- A primary CPU PCB that has the entire CPU, plus display/logic analyzer outputs.
+
+  ![](/images/IMG_7430.jpeg)
+
+  ![](/images/IMG_7434.jpeg)
+
+A second PCB implements the 'computer' support around the CPU including boot FLASH and System RAM.
+
+  ![](/images/IMG_7431.jpeg)
+
+   ![](/images/IMG_7435.jpeg)
+
+## Schematics
+
+There are DIPTRACE format schmatics in the CPUKIT_ASBUILT/schematics folder. 
+
+## CPLD
+
+The CPLD source code is located in the CPUKIT_ASBUILT/PLD folder.
+
+## Operations
+
+
+
+
+
+
+
+