Support for EffAdd A2D Routing in SP

CPUKit/PLD/IRCTRL/IRCTRL.PLD

@@ -144,12 +144,13 @@ Pin[21] = SHFT_WC;
 Pin[69] = HALTOREXEC;
 Pin[68] = SHFT_INVERTCARRY;
 Pin[76] = D2A_OE;
+Pin[75] = A2D_OE;    /* SP Module connect address bus inputs to data bus output.  Used for getting effective address */
 
 /* Unused pins, reserved for future use */
 
 Pin[65] = UNUSED1;
 Pin[74] = UNUSED2;
-Pin[75] = UNUSED3;
+
 
 Pin[77] = UNUSED5;
 Pin[79] = UNUSED6;
@@ -287,6 +288,8 @@ SHFT_INVERTCARRY.ck = A_CLK_IN;
 SHFT_INVERTCARRY.ap = !RESET_IN;
 D2A_OE.ck = A_CLK_IN;
 D2A_OE.ap = !RESET_IN;
+A2D_OE.ck = A_CLK_IN;
+A2D_OE.ap = !RESET_IN;
 
 
 
@@ -638,6 +641,8 @@ JMPINST.d = !(INST_ALL_JMP);
 HALT.d = !( INST_HALT );     
 D2A_OE.d = !(INST_RET_2);
 
+A2D_OE.d = 'b'1;
+
 /*
 Total dedicated input used:	4/4 	(100%)
 Total I/O pins used		64/64 	(100%)

CPUKit/PLD/REGFILE8/REGFILE8.PLD

@@ -85,6 +85,12 @@ PINNODE = REGWRITE;
 REGWRITE = !C_WE;   /* If this ==1, we are doing a regular register write, if ==0 no write  */
 
 
+/* 
+   For each of the 8 internal registers (RA,RB..RH), the input to that register is controlled by the REGWRITE flag, 
+   which is the invert of the C_WE input pin.  If REGWRITE is 1 AND creg has selected this register we will 
+   load the register from the CBUS.  If either REGWRITE is not 1, or creg has selected a different register we 
+   will loop back what is currently in the register (thus not changing it)
+*/
 [RAB0..7].ck = D_CLK_IN;
 [RAB0..7].ar = !ResetIN;
 RAB0.d = (REGWRITE & creg:['d'0] & CBUS0 & C_ZH ) # (!(REGWRITE & creg:['d'0]) & RAB0);

CPUKit/PLD/SP/SP.PLD

@@ -8,8 +8,6 @@ Assembly None;
 Location None;
 Device   f1508ispplcc84;
 
-
-
 PROPERTY ATMEL {TDI_PULLUP = ON};
 PROPERTY ATMEL {TMS_PULLUP = ON};
 PROPERTY ATMEL {PREASSIGN = KEEP};
@@ -24,6 +22,7 @@ Pin[1] = RESET_IN;
 Pin[2] = ADBUS_IB_OE;       /* An active low signal to replicate the BBUS input onto the ADBUS output */
 Pin[45,44]  = [SP_MODE0..1];
 Pin[79] = D2B_OE;
+Pin[80] = A2D_OE;
 
 /* Bidirectional Pins */
 
@@ -36,23 +35,27 @@ Pin[50] = AD0;              /* Bit 0 of the BBUS used to determine if we are doi
 
 /* Stuff for IR2 |||||| */
 Pin[54,55,57,58,56,61,63,60,64,65,67,73,74,75,77,76] = [DABUS0..15];
+[DABUS0..15].oe = !A2D_OE;
+[DABUS1..15] = [ADBUS1..15].io;
+DABUS0 = 'd'0;
+
+
 Pin[49] = IR2_LATCH;
 Pin[46] = IR2_OE;           /* Active low puts IR2 on BBUS */
 
 Pin[68] = UNUSED1;
 Pin[69] = UNUSED2;
 Pin[70] = UNUSED3;
-Pin[80] = UNUSED5;
-Pin[81] = UNUSED6;
 
-UNUSED1 = UNUSED2 # UNUSED3 # UNUSED5 # UNUSED6;
+Pin[81] = UNUSED6;
 
+UNUSED1 = UNUSED2 # UNUSED3 # UNUSED6;
 
 PINNODE = [IRTWO0..15];
 
 [IRTWO0..15].ck = D_CLK_IN;
 [IRTWO0..15].ar = !RESET_IN;
-[IRTWO0..15].d = (IR2_LATCH & [IRTWO0..15]) # (!IR2_LATCH & [DABUS0..15]);
+[IRTWO0..15].d = (IR2_LATCH & [IRTWO0..15]) # (!IR2_LATCH & [DABUS0..15].io);
 
 /* Stuff for IR2 ^^^^^^  */
 
@@ -69,7 +72,7 @@ PINNODE = [C2..C15];
 
 /* Pick the BBUS output from either SP or IR2 */
 
-[BBUS0..15] = (IR2_OE & D2B_OE & [SP0..15]) # ( !IR2_OE & [IRTWO0..15]) # (!D2B_OE & [DABUS0..15]);
+[BBUS0..15] = (IR2_OE & D2B_OE & [SP0..15]) # ( !IR2_OE & [IRTWO0..15]) # (!D2B_OE & [DABUS0..15].io);
 
 AD0 = BBUS0.io;
 A0_HOLD = 'b'0;