Skip to content

Commit

Permalink
cranelift: Delete more unused regalloc-related stuff
Browse files Browse the repository at this point in the history 
Part of the ongoing saga of bytecodealliance#8524, bytecodealliance#8566, bytecodealliance#8581, and bytecodealliance#8592
  • Loading branch information
@jameysharp
jameysharp committed May 13, 2024
1 parent 895a5ac commit 915afb4
Show file tree
Hide file tree
Showing 15 changed files with 343 additions and 409 deletions.
107 changes: 48 additions & 59 deletions cranelift/codegen/src/isa/aarch64/inst/emit.rs
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7867,7 +7867,7 @@ fn test_aarch64_binemit() {
assert_eq!(expected_printing, actual_printing);

let mut buffer = MachBuffer::new();
insn.emit(&[], &mut buffer, &emit_info, &mut Default::default());
insn.emit(&mut buffer, &emit_info, &mut Default::default());
let buffer = buffer.finish(&Default::default(), &mut Default::default());
let actual_encoding = &buffer.stringify_code_bytes();
assert_eq!(expected_encoding, actual_encoding);
Expand Down
271 changes: 124 additions & 147 deletions cranelift/codegen/src/isa/riscv64/inst/emit.rs
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2114,7 +2114,7 @@ fn test_riscv64_binemit() {
assert_eq!(unit.assembly, actual_printing);
let mut buffer = MachBuffer::new();
unit.inst
.emit(&[], &mut buffer, &emit_info, &mut Default::default());
.emit(&mut buffer, &emit_info, &mut Default::default());
let buffer = buffer.finish(&Default::default(), &mut Default::default());
let actual_encoding = buffer.stringify_code_bytes();

Expand Down Expand Up @@ -2201,7 +2201,7 @@ fn riscv64_worst_case_instruction_size() {
let mut max: (u32, MInst) = (0, Inst::Nop0);
for i in candidates {
let mut buffer = MachBuffer::new();
i.emit(&[], &mut buffer, &emit_info, &mut Default::default());
i.emit(&mut buffer, &emit_info, &mut Default::default());
let buffer = buffer.finish(&Default::default(), &mut Default::default());
let length = buffer.data().len() as u32;
if length > max.0 {
Expand Down
47 changes: 20 additions & 27 deletions cranelift/codegen/src/isa/s390x/inst/emit.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@ use crate::isa::s390x::inst::*;
use crate::isa::s390x::settings as s390x_settings;
use crate::trace;
use cranelift_control::ControlPlane;
use regalloc2::Allocation;

/// Debug macro for testing that a regpair is valid: that the high register is even, and the low
/// register is one higher than the high register.
Expand Down Expand Up @@ -181,7 +180,7 @@ pub fn mem_emit(
},
);
for inst in mem_insts.into_iter() {
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

if add_trap {
Expand Down Expand Up @@ -244,7 +243,7 @@ pub fn mem_rs_emit(
},
);
for inst in mem_insts.into_iter() {
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

if add_trap {
Expand Down Expand Up @@ -295,7 +294,7 @@ pub fn mem_imm8_emit(
},
);
for inst in mem_insts.into_iter() {
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

if add_trap {
Expand Down Expand Up @@ -342,7 +341,7 @@ pub fn mem_imm16_emit(
},
);
for inst in mem_insts.into_iter() {
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

if add_trap {
Expand Down Expand Up @@ -412,7 +411,7 @@ pub fn mem_vrx_emit(
},
);
for inst in mem_insts.into_iter() {
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

if add_trap {
Expand Down Expand Up @@ -1364,17 +1363,11 @@ impl MachInstEmit for Inst {
type State = EmitState;
type Info = EmitInfo;

fn emit(
&self,
_allocs: &[Allocation],
sink: &mut MachBuffer<Inst>,
emit_info: &Self::Info,
state: &mut EmitState,
) {
fn emit(&self, sink: &mut MachBuffer<Inst>, emit_info: &Self::Info, state: &mut EmitState) {
self.emit_with_alloc_consumer(sink, emit_info, state)
}

fn pretty_print_inst(&self, _allocs: &[Allocation], state: &mut EmitState) -> String {
fn pretty_print_inst(&self, state: &mut EmitState) -> String {
self.print_with_state(state)
}
}
Expand Down Expand Up @@ -1450,7 +1443,7 @@ impl Inst {
ri: rn,
rm,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
} else {
put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0));
}
Expand All @@ -1468,7 +1461,7 @@ impl Inst {
ri: rn,
imm,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
} else {
let opcode = match alu_op {
ALUOp::Add32 => 0xecd8, // AHIK
Expand Down Expand Up @@ -2053,7 +2046,7 @@ impl Inst {
target: loop_label,
cond,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);

// Emit label at the end of the loop.
sink.bind_label(done_label, &mut state.ctrl_plane);
Expand Down Expand Up @@ -2240,7 +2233,7 @@ impl Inst {
&Inst::MovPReg { rd, rm } => {
let rm: Reg = rm.into();
debug_assert!([regs::gpr(0), regs::gpr(14), regs::gpr(15)].contains(&rm));
Inst::Mov64 { rd, rm }.emit(&[], sink, emit_info, state);
Inst::Mov64 { rd, rm }.emit(sink, emit_info, state);
}
&Inst::Mov32 { rd, rm } => {
let opcode = 0x18; // LR
Expand Down Expand Up @@ -2360,7 +2353,7 @@ impl Inst {
rd,
mem: MemArg::reg(reg, MemFlags::trusted()),
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

&Inst::FpuMove32 { rd, rn } => {
Expand Down Expand Up @@ -2422,7 +2415,7 @@ impl Inst {
mem: MemArg::reg(reg, MemFlags::trusted()),
lane_imm: 0,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}
&Inst::LoadFpuConst64 { rd, const_data } => {
let opcode = 0xa75; // BRAS
Expand All @@ -2435,7 +2428,7 @@ impl Inst {
mem: MemArg::reg(reg, MemFlags::trusted()),
lane_imm: 0,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}
&Inst::FpuRR { fpu_op, rd, rn } => {
let (opcode, m3, m4, m5, opcode_fpr) = match fpu_op {
Expand Down Expand Up @@ -2846,7 +2839,7 @@ impl Inst {
rn,
rm,
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}

&Inst::VecLoad { rd, ref mem }
Expand Down Expand Up @@ -2939,7 +2932,7 @@ impl Inst {
rd,
mem: MemArg::reg(reg, MemFlags::trusted()),
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}
&Inst::VecLoadConstReplicate {
size,
Expand All @@ -2957,7 +2950,7 @@ impl Inst {
rd,
mem: MemArg::reg(reg, MemFlags::trusted()),
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);
}
&Inst::VecImmByteMask { rd, mask } => {
let opcode = 0xe744; // VGBM
Expand Down Expand Up @@ -3356,7 +3349,7 @@ impl Inst {
target: table_label,
},
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);

// Set temp to target address by adding the value of the jump table entry.
let inst = Inst::AluRX {
Expand All @@ -3365,15 +3358,15 @@ impl Inst {
ri: rtmp.to_reg(),
mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()),
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);

// Branch to computed address. (`targets` here is only used for successor queries
// and is not needed for emission.)
let inst = Inst::IndirectBr {
rn: rtmp.to_reg(),
targets: vec![],
};
inst.emit(&[], sink, emit_info, state);
inst.emit(sink, emit_info, state);

// Emit jump table (table of 32-bit offsets).
sink.bind_label(table_label, &mut state.ctrl_plane);
Expand Down
2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/s390x/inst/emit_tests.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13375,7 +13375,7 @@ fn test_s390x_binemit() {
buffer.bind_label(label0, ctrl_plane);

// Emit the instruction.
insn.emit(&[], &mut buffer, &emit_info, &mut Default::default());
insn.emit(&mut buffer, &emit_info, &mut Default::default());

// Label 1 after the instruction.
let label1 = buffer.get_label();
Expand Down
11 changes: 4 additions & 7 deletions cranelift/codegen/src/isa/s390x/inst/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2096,9 +2096,8 @@ impl Inst {
format!("vlr {}, {}", rd, rn)
}
}
&Inst::FpuCMov32 { rd, cond, ri, rm } => {
&Inst::FpuCMov32 { rd, cond, rm, .. } => {
let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg());
let _ri = ri;
let (rm, rm_fpr) = pretty_print_fpr(rm);
if rd_fpr.is_some() && rm_fpr.is_some() {
let cond = cond.invert().pretty_print_default();
Expand All @@ -2108,9 +2107,8 @@ impl Inst {
format!("j{} 10 ; vlr {}, {}", cond, rd, rm)
}
}
&Inst::FpuCMov64 { rd, cond, ri, rm } => {
&Inst::FpuCMov64 { rd, cond, rm, .. } => {
let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg());
let _ri = ri;
let (rm, rm_fpr) = pretty_print_fpr(rm);
if rd_fpr.is_some() && rm_fpr.is_some() {
let cond = cond.invert().pretty_print_default();
Expand Down Expand Up @@ -2822,16 +2820,16 @@ impl Inst {
&Inst::VecLoadLane {
size,
rd,
ri,
ref mem,
lane_imm,
..
}
| &Inst::VecLoadLaneRev {
size,
rd,
ri,
ref mem,
lane_imm,
..
} => {
let opcode_vrx = match (self, size) {
(&Inst::VecLoadLane { .. }, 8) => "vleb",
Expand All @@ -2845,7 +2843,6 @@ impl Inst {
};

let (rd, _) = pretty_print_fpr(rd.to_reg());
let _ri = ri;
let mem = mem.clone();
let (mem_str, mem) = mem_finalize_for_show(
&mem,
Expand Down
Loading

0 comments on commit 915afb4

Please sign in to comment.