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Fix issue in prefetching column major matrix. #4611

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Merged
whitneywhtsang merged 8 commits into from
Jul 14, 2025
Merged

Fix issue in prefetching column major matrix. #4611

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1e9fd7e
Fix issue in prefetching column major matrix.
chengjunlu Mar 10, 2025
4c69c8a
Merge branch 'main' into chengjun/fix_prefetch_issue
whitneywhtsang Jul 10, 2025
31b7bca
Merge branch 'main' into chengjun/fix_prefetch_issue
whitneywhtsang Jul 10, 2025
ab0f713
Merge branch 'main' into chengjun/fix_prefetch_issue
etiotto Jul 11, 2025
8a4287d
[TritonGEN] Lower to GenISA for `2d_block_prefetch_16b_16r8x1c`
whitneywhtsang Jul 11, 2025
18c95b9
Merge branch 'main' into chengjun/fix_prefetch_issue
whitneywhtsang Jul 11, 2025
dd3888a
Merge branch 'main' into chengjun/fix_prefetch_issue
chengjunlu Jul 14, 2025
a73a5d9
Merge branch 'main' into chengjun/fix_prefetch_issue
chengjunlu Jul 14, 2025
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10 changes: 5 additions & 5 deletions test/TritonIntelGPU/prefetch-to-llvm.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -73,10 +73,10 @@ module attributes {"ttg.num-warps" = 8 : i32, "ttg.threads-per-warp" = 16 : i32}
// CHECK: %[[SUB_GROUP_ID_RAW:.*]] = llvm.call spir_funccc @_Z16get_sub_group_id() {no_unwind, will_return} : () -> i32
// CHECK: %[[SUB_GROUP_ID_EXT:.*]] = llvm.zext %[[SUB_GROUP_ID_RAW]] : i32 to i64
// CHECK: %[[SUB_GROUP_ID:.*]] = llvm.trunc %[[SUB_GROUP_ID_EXT]] : i64 to i32
// CHECK: %[[VAL_18:.*]] = llvm.mlir.constant(2 : i32) : i32
// CHECK: %[[VAL_18:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK: %[[VAL_19:.*]] = llvm.urem %[[SUB_GROUP_ID]], %[[VAL_18]] : i32
// CHECK: %[[VAL_20:.*]] = llvm.udiv %[[SUB_GROUP_ID]], %[[VAL_18]] : i32
// CHECK: %[[CST_8:.*]] = llvm.mlir.constant(4 : i32) : i32
// CHECK: %[[CST_8:.*]] = llvm.mlir.constant(8 : i32) : i32
// CHECK: %[[VAL_22:.*]] = llvm.urem %[[VAL_20]], %[[CST_8]] : i32
// CHECK: %[[VAL_23:.*]] = llvm.udiv %[[VAL_20]], %[[CST_8]] : i32
// CHECK: %[[OFFSET_0:.*]] = llvm.extractvalue %[[BLOCK_POINTER]][0] : !llvm.struct<(i32, i32, i64, i64, i64, i64, ptr<1>)>
Expand All @@ -94,20 +94,20 @@ module attributes {"ttg.num-warps" = 8 : i32, "ttg.threads-per-warp" = 16 : i32}
// CHECK: %[[VAL_24:.*]] = llvm.mul %[[COL_STRIDE_i64]], %[[CST_2]] : i64
// CHECK: %[[COL_MAJOR_PITCH:.*]] = llvm.trunc %[[VAL_24]] : i64 to i32
// CHECK: %[[CST_0:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST_32:.*]] = llvm.mlir.constant(16 : i32) : i32
// CHECK: %[[CST_32:.*]] = llvm.mlir.constant(32 : i32) : i32
// CHECK: %[[VAL_26:.*]] = llvm.mul %[[VAL_19]], %[[CST_32]] : i32
// CHECK: %[[VAL_27:.*]] = llvm.add %[[VAL_26]], %[[CST_0]] : i32
// CHECK: %[[CST_32:.*]] = llvm.mlir.constant(32 : i32) : i32
// CHECK: %[[VAL_28:.*]] = llvm.urem %[[VAL_27]], %[[CST_32]] : i32
// CHECK: %[[COL_MAJOR_OFFSET_X:.*]] = llvm.add %[[VAL_28]], %[[OFFSET_1]] : i32
// CHECK: %[[CST_0:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST_2:.*]] = llvm.mlir.constant(4 : i32) : i32
// CHECK: %[[CST_2:.*]] = llvm.mlir.constant(2 : i32) : i32
// CHECK: %[[VAL_30:.*]] = llvm.mul %[[VAL_22]], %[[CST_2]] : i32
// CHECK: %[[VAL_31:.*]] = llvm.add %[[VAL_30]], %[[CST_0]] : i32
// CHECK: %[[CST_16:.*]] = llvm.mlir.constant(16 : i32) : i32
// CHECK: %[[VAL_32:.*]] = llvm.urem %[[VAL_31]], %[[CST_16]] : i32
// CHECK: %[[COL_MAJOR_OFFSET_Y:.*]] = llvm.add %[[VAL_32]], %[[OFFSET_0]] : i32
// CHECK: triton_gen.2Dblockprefetch %[[BASE_]], %[[COL_MAJOR_BASE_WIDTH]], %[[COL_MAJOR_BASE_HEIGHT]], %[[COL_MAJOR_PITCH]], %[[COL_MAJOR_OFFSET_X]], %[[COL_MAJOR_OFFSET_Y]] {elem_size_in_bits = 16, tile_width = 16, tile_height = 4, v_blocks = 1, cache_control = L1C_L3C}
// CHECK: triton_gen.2Dblockprefetch %[[BASE_]], %[[COL_MAJOR_BASE_WIDTH]], %[[COL_MAJOR_BASE_HEIGHT]], %[[COL_MAJOR_PITCH]], %[[COL_MAJOR_OFFSET_X]], %[[COL_MAJOR_OFFSET_Y]] {elem_size_in_bits = 16, tile_width = 16, tile_height = 2, v_blocks = 2, cache_control = L1C_L3C}
%columnMajorPtr = tt.make_tensor_ptr %arg0, [%arg4, %arg2], [%c1_i64, %arg5], [%c0_i32, %c0_i32] {order = array<i32: 0, 1>} : <tensor<32x16xf16>>
ttig.prefetch %columnMajorPtr {cache = 1 : i32, evict = 1 : i32, isVolatile = false, ttig.block_io = "column_major"} : !tt.ptr<tensor<32x16xf16>>

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4 changes: 4 additions & 0 deletions third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -559,6 +559,10 @@ struct PrefetchOpConversion
// Swap the shape to make it row major and then get the tiling
// size base on row major shape.
std::swap(tensorShape[0], tensorShape[1]);

// Create the new tensor type with swapped row and col.
tensorType = RankedTensorType::get(
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tensorShape, tensorType.getElementType(), tensorType.getEncoding());
}

unsigned numWarps = triton::gpu::lookupNumWarps(op);
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