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Computer-Architecture-RISC-V

  • RISC-V core design using VerilogHDL
  • KECE343 Computer Architecture (Prof. Seon Wook Kim)
  • Use “real-world” examples to illustrate important concept of computer architecture
    • Four projects using RISC-V

Overview

Use a 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM (reference)

RISC-V Core Architecture

image

  • 32-bit RISC-V ISA CPU core
  • Support RISC-V integer(I), multiplication and division (M), and CSR instructions, (Z) extensions (RV32IMZicsr)
  • Support for instruction / data cache, AXI bus interfaces or tightly coupled memories

Project 1: RISC-V core design using Verilog & Project environment setting

GOAL: Project Environment Setting

  • Set project environment based on ModelSim-Intel FPGA Edition
  • Install Cygwin & RISC-V cross compiler
  • Write a simple test code and verify execution
    • Calculate CPI
  • Draw and describe block diagram of RISC-V core by analyzing the given code

Project 2: Memory hierarchy & Cache design

GOAL: Understand Memory Hierarchy and Cache Architecture
image

  • Analyze the operation of the cache in the form of waveform
    • FSM of cache controller
    • debug_cache_eviction_trace.txt
  • Modify cache size to given conditions and analyze results (verify performance improvement)
    • D-cache: 2-way set associative 16K byte size, block granularity: 32 byte -> x2 cache block size
    • Explain modified verilog source code
    • debug_cache_hit_count_trace.txt, debug_doubled_cache_hit_count_trace.txt
    • Caculate hit ratio

Project 3: HPC (Hardware Performance counter) design

GOAL: Understand Performance Methodolgy & Metric of RISC-V core

  • RISC-V registers & calling convention
    • Explain the change in the stack layout of functions and the entire stack when each function is executed in the function calling sequence
    • Verify and explain register values in the form of waveform
  • Design HPC which measure performance metric
    • Explain HPC verilog source code
  • Verify the operation of pipelining and analyze results (verify pipeline stall)

Project 4: Instruction set extension design

GOAL: Understand Data Path & Control Path of Instructions by each pipeline stages of RISC-V core

  • Understand RISC-V ISA
  • Design extended ISA in RTL-level and verify it through testbench

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