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14 Open 2 Closed
14 Open 2 Closed
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Issues list

Synthesis failed
#17 opened Mar 11, 2024 by gzzyyxh
Demo is unavailable
#16 opened Jan 20, 2024 by gzzyyxh
Could not find /dev/xdma0_user
#15 opened Apr 1, 2022 by Ayden-hnliu
1
Some DSP area constraints are over utilized
#13 opened May 24, 2020 by nazarihome
FileNotFoundError: [Errno 2] No such file or directory: '/dev/xdma0_user'
#12 opened Mar 24, 2020 by HemantaIngle
1
OverflowError: Python int too large to convert to C long
#11 opened Mar 24, 2020 by HemantaIngle
1
MMAP OSError: [Errno 22] Invalid argument
#10 opened Dec 20, 2019 by Morett07
3
AttributeError: 'collections.OrderedDict' object has no attribute 'iteritems'
#9 opened Oct 21, 2019 by Hassan313
porting dnnweaver to xilinx zynq xc7z020 board，I have encountered some problems.
#8 opened Sep 23, 2019 by zhang007z
cl_wrapper: Incompatible Module
#7 opened Jun 25, 2019 by faromero
2
Example or Tutorial
#5 opened May 3, 2019 by elizamanelli
1
Can you provide for the rtl testbench？
#4 opened Apr 11, 2019 by wxbbuaa2011
1
modifing c0_ddr4_ui_clk ???
#3 opened Jan 24, 2019 by xiaoguoer
1
Is this only for PCIe connection or could be connected to AXI buses (on Zynq) directly?
#1 opened Nov 14, 2018 by Pe3ucTop
12
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