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When trying to add the cl_wrapper module, I get an Incompatible Module issue that prevents me from adding it. I also see that obuf, pe, banked_ram, obuf_mem_wrapper, mux_n_1, signed_adder, systolic_array, and dnnweaver2_controller are deemed to be incompatible, so I am guessing by virtue of them not being compatible, it prevents the top-level module from being compatible. I am using Vivado 2018.3.
The text was updated successfully, but these errors were encountered:
I had the same issue, it seems to be caused by a recursive module inside cl_wrapper.
I solved it by packaging the cl_wrapper module as an IP, then it was visible in the library as classical Xilinx IP and I managed to add it to the block diagram.
Hi @faromero
I met this problem too(using 2018.3), I solved this by changing the version of vivado to 2018.2 and this problem auto disappeared. Hope this can help u.
When trying to add the cl_wrapper module, I get an Incompatible Module issue that prevents me from adding it. I also see that obuf, pe, banked_ram, obuf_mem_wrapper, mux_n_1, signed_adder, systolic_array, and dnnweaver2_controller are deemed to be incompatible, so I am guessing by virtue of them not being compatible, it prevents the top-level module from being compatible. I am using Vivado 2018.3.
The text was updated successfully, but these errors were encountered: