[Performance][DeepSeek-V4] Qualify A100 sparse decode launches for FULL CUDA graphs

[haosdent]

CODE-AGENT-GENERATED DRAFT — DO NOT MARK READY OR MERGE. A human has
not line-reviewed this diff, independently accepted the measurements, or
taken maintenance ownership. The checklist at the end remains mandatory.

Purpose

Apply two measured DeepSeek-V4 sparse-decode launch configurations on A100 and
make those choices effective in default pure-decode FULL CUDA graphs.

This is a three-commit SM80 launch-policy series stacked on the DeepSeek-V4
A100 support foundation. It does not add model support or a new attention
backend, and it does not claim an end-to-end TTFT, TPOT, ITL, or throughput
improvement.

The current frozen serving candidate is not this PR in isolation or the exact
open-PR union. It also contains #11-style custom-all-reduce sizing, SM80
prefill tuning, and unpublished compressed-indexer-width commit f7dd6c5634;
#12 and vllm-project#50645 are common to both frozen arms. Concurrency-one decode uses q1,
which this PR deliberately leaves on fallback. Shared-c64 is relevant to the
q64 entry, but remains composed evidence and cannot be attributed to this PR.

Exact publication scope

• Local branch: pr/deepseek-v4-a100-decode-dedup
• Fork head ref: deepseek-v4-a100-decode-dedup
• Head: a3a0124c822a9cc662d079558649d34cb4e91639
• Direct stack base:
  deepseek-v4-a100-support-dedup-v2@464244e46c6657a84799dc1d4eee7c6bc96798d4
• Diff against the direct base: five files, +830/-47

The three commits are:

1. 4ae1cb4c07512705548d408a9080e3647ba9fac4
perf: apply measured SM80 sparse decode launches
2. 1aecf537934326f1725bb700deeb2d8905f64835
perf: activate qualified SM80 decode launches in full graphs
3. a3a0124c822a9cc662d079558649d34cb4e91639
refactor: trim SM80 sparse decode launch policy

Runtime changes are limited to the DeepSeek-V4 portable sparse-decode wrapper,
its metadata builder, and a new 161-line launch-policy module. The other two
changed files are focused tests.

Duplicate and adjacent-work audit

The following exact GitHub PR searches were run on 2026-08-03 UTC, followed by
inspection of the candidate file patches:

Query	Results	Relevant candidates
repo:vllm-project/vllm is:pr "DeepSeek V4" A100 decode	9	vllm-project#47629, vllm-project#38476, vllm-project#40906
repo:vllm-project/vllm is:pr SM80 "sparse MLA"	10	vllm-project#47629, vllm-project#38476, vllm-project#41834, vllm-project#40906
repo:vllm-project/vllm is:pr "compressed indexer" decode logits	5	vllm-project#38476, vllm-project#41834
repo:vllm-project/vllm is:pr max_seq_len compress_ratio indexer	1	vllm-project#41834

The audit changed the publication scope:

• [Attention] TRITON_MLA_SPARSE backend for SM80/SM121 sparse MLA (rebase & takeover of #38476) vllm-project/vllm#47629, the takeover of [Feature] TRITON_MLA_SPARSE backend for SM8x/11x/12x DSA Sparse MLA Support vllm-project/vllm#38476, implements the general SM80/SM121 Triton
  sparse-MLA and indexer fallback. This series tunes exact launches only after
  that shared backend is present; it does not replace it.
• [New Model][Nvidia] Add SM12x support for DeepSeek V4 Flash with essential fixes vllm-project/vllm#41834 already implements the compressed indexer-decode width outcome by a
  different method in a broader SM12x series. The local compressed-width
  commit was therefore deliberately excluded from this PR. This publication
  branch contains no indexer-width change.
• [WIP][New Model] Add A100/SM80 support for DeepSeek V4 Flash vllm-project/vllm#40906 is a closed broad A100/SM80 proof-of-concept.
• [ROCm][Performance] Eliminate per-decode allocations and output copy … vllm-project/vllm#50566 is open adjacent work in the same sparse-decode files. It preallocates
  split-K buffers and removes the final output copy. It does not add the exact
  q64/q128 launch table or FULL-graph routing in this series, but it is likely
  to conflict textually and should be benchmarked together after rebase.

No inspected candidate contained the exact combination of the retained q64 and
q128 A100 launch entries plus the pure-decode FULL CUDA-graph capture policy.
The direct support base is now the deduplicated DeepSeek-V4-only consumer in
draft PR #15, itself stacked on the exact vllm-project#47629 head. Keep this PR stacked on
PR #15 so its Files tab remains the five-file launch-policy delta.

Changed behavior

Exact measured SM80 launches

Architecture dispatch is exact. Only the exact SM80 split-K route can consult
the measured table, and the table contains only these A100-SXM4-80GB shapes:

Decode shape (queries, heads, main, extra, SMs)	Launch
(64, 8, 128, 512, 108)	BLOCK_H=8, BLOCK_K=32, splits=3, warps=4
(128, 8, 128, 512, 108)	BLOCK_H=8, BLOCK_K=32, splits=4, warps=8

q1, q8, and q32 were measured and rejected. Every unlisted batch size, head
count, row length, fractional/ragged average, SM count, architecture, and model
configuration returns the caller's deployed fallback unchanged.

The offline 192-configuration sweep, occupancy estimator, selection
dataclasses, and margin gate were removed from runtime source after reducing
the winner set to these two exact keys. The benchmark method and raw samples
remain outside serving code.

FULL CUDA-graph capture

The previous host-side full-row proof works in eager and piecewise execution,
where metadata construction sees live sequence lengths. Default pure-decode
FULL graph capture instead observes short dummy sequence lengths, so it
captured the fallback launch. CUDA graph replay cannot later switch the
captured nodes to a different Triton specialization.

For an eligible exact-SM80, ratio-4, causal, non-speculative DeepSeek-V4 decode
configuration, the metadata builder now pins measured-policy eligibility while
capturing a pure FULL decode graph. The exact table lookup remains the final
gate, so only q64 and q128 capture a measured launch; q1, q8, q32, and all other
misses still capture the fallback. Eager, piecewise, and mixed prefill/decode
execution retain the runtime full-length proof.

A real-A100 test forces both retained launches over short, uneven replay rows
and compares them with the reference. Noncausal decode, speculative decode,
different window/top-k/compression settings, non-SM80 devices, and non-108-SM
devices remain excluded.

Production-wrapper measurements

These are wrapper/kernel measurements on one NVIDIA A100-SXM4-80GB (SM80,
108 SMs), not model-serving results. q is the number of decode queries, not
the context length.

The benchmark called the production sparse-decode wrapper with block size 64,
distinct sequential slots, production cache layout [num_blocks, 64, 584],
and full rows of 128 main plus 512 extra entries. Each arm received 20 warmups;
seven rounds alternated arm order; each arm timed 50 launches with CUDA events.
Values below are the median of the seven per-arm means.

q	Deployed fallback	Candidate	Change vs fallback	Decision
1	116.982 us	121.549 us	-3.90%	Rejected
8	116.285 us	120.074 us	-3.26%	Rejected
32	115.302 us	120.095 us	-4.16%	Rejected
64	189.235 us	169.595 us	+10.38%	Retained
128	370.463 us	321.516 us	+13.21%	Retained

The late q128 arms showed a common device-state shift in both policies. The
median remained in the earlier cluster and the relative ordering persisted,
but this reinforces the requirement for repeated model-serving A/Bs.

Full 128-main/512-extra rows are relevant once the long-context index sets are
saturated, including the intended 128K and 256K scenarios. This wrapper did
not itself execute a 128K or 256K model request, so these results must not be
reported as TTFT, TPOT, ITL, or throughput gains.

Verification evidence

Exact publication head

The CPU-only policy, dispatch, graph-selection, and 128K/256K boundary suite
was rerun on 2026-08-03 at exact rebased head
a3a0124c822a9cc662d079558649d34cb4e91639:

cd /root/vllm-pr-worktrees/publish-dsv4-a100-decode-dedup
CUDA_VISIBLE_DEVICES='' /root/vllm/.venv/bin/python -m pytest \
  tests/v1/attention/test_dsv4_sparse_decode_launch.py -q

Result: 43 passed.

The changed-file hooks were also rerun on that exact head:

cd /root/vllm-pr-worktrees/publish-dsv4-a100-decode-dedup
/root/vllm-venv/bin/pre-commit run \
  --from-ref 464244e46c6657a84799dc1d4eee7c6bc96798d4 \
  --to-ref a3a0124c822a9cc662d079558649d34cb4e91639
git diff --check \
  464244e46c6657a84799dc1d4eee7c6bc96798d4..HEAD

All applicable hooks passed, including Ruff, mypy, SPDX, forbidden-import,
configuration, and repository policy checks. git diff --check was clean, and
the publication worktree remained clean at the same head.

A100 replay cases on the rebased head

The two actual A100 short/uneven replay cases were rerun on the exact rebased
publication head:

cd /root/vllm-pr-worktrees/publish-dsv4-a100-decode-dedup
CUDA_VISIBLE_DEVICES=7 PYTHONPATH=$PWD \
  /root/vllm/.venv/bin/python -m pytest \
  tests/kernels/attention/test_rocm_triton_attn_dsv4.py::test_measured_sm80_decode_launch_is_safe_for_short_graph_replay -q

Result: 2 passed in 5.33 s on the 108-SM A100.

Model evaluation status

Not yet run as a paired model-serving A/B on this exact publication series.
The CPU policy suite covers 128K/256K full-length proof and graph selection,
but no full-model baseline/patched comparison is available for either context
length.

Before this PR is promoted, run repeated baseline-versus-patched serving tests
at 128K and 256K with identical prompts, concurrency, CUDA-graph batch sizes,
clock/power state, cache state, output length, and server flags. Report:

• TTFT distribution;
• client TPOT and server-side per-request mean ITL;
• exact per-token ITL percentiles only if a non-coalescing server-side trace is
  added and its overhead is characterized;
• request and token throughput;
• output correctness and run-to-run variance; and
• long-context retrieval plus generation quality.

Until that evidence is attached, the honest claims are limited to the
graph-routing correction, focused correctness tests, and q64/q128 wrapper
timings above.

Risks and limitations

• The measured target was A100-SXM4-80GB. Dispatch gates on SM80 capability
  and 108 SMs, not product identity, so another 108-SM SM80 product could take
  the entries without having been independently measured.
• The launch tuning benefits only exact q64/q128 full-row shapes. Lower
  concurrency and every table miss deliberately retain the deployed fallback.
• The concurrency-one frozen workload therefore cannot validate this launch
  table, and the shared-c64 workload does not isolate it from other candidate
  changes.
• Short-row replay safety is tested at kernel level, but full-model graph
  correctness and long-context quality remain pending.
• [ROCm][Performance] Eliminate per-decode allocations and output copy … vllm-project/vllm#50566 touches the same decode wrapper. Final code and benchmark results can
  change after the required rebase/composition test.
• No 128K/256K server performance result is currently available.

Stack and review order

1. Rebase and resolve the same-file interaction with [ROCm][Performance] Eliminate per-decode allocations and output copy … vllm-project/vllm#50566.
2. Rerun the 43 CPU cases, two A100 cases, and changed-file hooks on the final
   hashes.
3. Attach an exact-PR-union paired 128K/256K model-serving comparison; do not
   reuse the composed working-bundle result as standalone evidence.
4. Only then request upstream review.

AI assistance and human ownership

This code series, benchmark analysis, verification summary, duplicate-work
audit, and PR-body draft were prepared with OpenAI Codex. No human
attestation has been recorded for the final diff, tests, measurements, or
maintenance ownership. Keep the GitHub PR in draft state until a human
completes and explicitly attests all of the following:

• @haosdent line-reviewed the final rebased diff.
• @haosdent reviewed or independently reran the reported tests and
  measurements on the final hashes.
• @haosdent understands the exact dispatch boundaries, FULL CUDA-graph
  behavior, numerical risk, and open PR conflicts.
• @haosdent accepts responsibility for the contribution and its ongoing
  maintenance.

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