compute-fabric refine: reconcile DESIGN §2 storage-anemia clause with the grounded NVMe PcieLink axis

DESIGN.md

@@ -32,7 +32,7 @@ Redundant work — **duplicated, unnecessary, or irrelevant** — loses on all t
 - **Horizontal — one concept, every scale and breadth.** Model a concept once; derive every use (model-local / derive-global). At the right layer there is nothing fundamentally different between scales, so the *same* concept spans nanosecond memoization and broad infra deployment — the Realization pattern (content-addressed pure-spec → host-effect; one kernel, N handlers).
   - *e.g.* `dsl/std/integer.dag`: `Int8`…`UInt128` are 10 `Compose<Int, MachineWidth<N>>` rows, one axis not 10 types. Realization spans resolve-cost (ns) → sccache → §10 OS provisioning on one content-hash. Cost of *not* doing it: eleven hand-rolled v1 `HashMap` caches, and v2 still recurs (`ParseTable`).
 - **Deep — every concept decomposed to grounded atoms.** Nothing is opaque that isn't *genuinely* atomic. The move is `decompress → map → reduce`: reveal the structure the source names, **map** each part onto the concept that already exists (DFS the concept DAG first), **reduce** duplicates. A `String` leaf hiding named parts is anemic modeling.
-  - *e.g.* `"LGA4926"` → `CpuSocket { package: LandGridArray, contact_count: 4926 }` (the number is a grounded `Int`) and `"HMA82GR7AFR4N-VK"` → `DramModuleCatalogRow { chip_width: bit_width(4), rank_count: 1, buffering: Registered }` (the numeric organization axes decoded from the part number ground into existing magnitudes — `chip_width` reuses `BitWidth`, `rank_count` is a cardinal `Int` — not a fresh enum re-inventing bit-width; the categorical axis stays a closed enum); `Cost = Time|Space|Energy` → a record (every cost has all three); still-anemic today: `product.compute_fabric`'s `StorageDevice` has no PCIe-gen/lane-count axis (storage's rank/width). (`GpuFacts.vendor`, once a bare `NonEmptyStr` where `CpuVendor` was a closed enum, is now grounded on the single `Vendor<Hardware>` authority — see §3.)
+  - *e.g.* `"LGA4926"` → `CpuSocket { package: LandGridArray, contact_count: 4926 }` (the number is a grounded `Int`) and `"HMA82GR7AFR4N-VK"` → `DramModuleCatalogRow { chip_width: bit_width(4), rank_count: 1, buffering: Registered }` (the numeric organization axes decoded from the part number ground into existing magnitudes — `chip_width` reuses `BitWidth`, `rank_count` is a cardinal `Int` — not a fresh enum re-inventing bit-width; the categorical axis stays a closed enum); `Cost = Time|Space|Energy` → a record (every cost has all three); and `"WDS200T2X0E"` → `NvmeDeviceCatalogRow { pcie_link: PcieLink { generation: Gen4, lane_count: 4 }, form_factor: M2_2280, .. }` (storage's rank/width: `lane_count` a cardinal `Int`, `PcieGeneration` a closed enum, per-lane bandwidth *derived* not stored — cited to the PCI Express authority in `extdeps/storage/types.dag` and surfaced through `product.compute_fabric`'s `StorageDevice.catalog`, parallel to the DRAM row above). (`GpuFacts.vendor`, once a bare `NonEmptyStr` where `CpuVendor` was a closed enum, is now grounded on the single `Vendor<Hardware>` authority — see §3.)
 
 The test that an edit actually *reduced* redundancy rather than moving it: **net concepts must not grow by re-invention.** Decomposing a leaf by minting a fresh authority for a concept that already exists is a failed decomposition.
 

dsl/gunbc/design_document.dag

@@ -66,7 +66,7 @@ fn section_2_blocks() -> List<MarkdownBlock> {
       li_blocks(blocks: [
         p(text: "**Deep — every concept decomposed to grounded atoms.** Nothing is opaque that isn't *genuinely* atomic. The move is `decompress → map → reduce`: reveal the structure the source names, **map** each part onto the concept that already exists (DFS the concept DAG first), **reduce** duplicates. A `String` leaf hiding named parts is anemic modeling."),
         ul(items: [
-          li(text: "*e.g.* `\"LGA4926\"` → `CpuSocket \{ package: LandGridArray, contact_count: 4926 \}` (the number is a grounded `Int`) and `\"HMA82GR7AFR4N-VK\"` → `DramModuleCatalogRow \{ chip_width: bit_width(4), rank_count: 1, buffering: Registered \}` (the numeric organization axes decoded from the part number ground into existing magnitudes — `chip_width` reuses `BitWidth`, `rank_count` is a cardinal `Int` — not a fresh enum re-inventing bit-width; the categorical axis stays a closed enum); `Cost = Time|Space|Energy` → a record (every cost has all three); still-anemic today: `product.compute_fabric`'s `StorageDevice` has no PCIe-gen/lane-count axis (storage's rank/width). (`GpuFacts.vendor`, once a bare `NonEmptyStr` where `CpuVendor` was a closed enum, is now grounded on the single `Vendor<Hardware>` authority — see §3.)"),
+          li(text: "*e.g.* `\"LGA4926\"` → `CpuSocket \{ package: LandGridArray, contact_count: 4926 \}` (the number is a grounded `Int`) and `\"HMA82GR7AFR4N-VK\"` → `DramModuleCatalogRow \{ chip_width: bit_width(4), rank_count: 1, buffering: Registered \}` (the numeric organization axes decoded from the part number ground into existing magnitudes — `chip_width` reuses `BitWidth`, `rank_count` is a cardinal `Int` — not a fresh enum re-inventing bit-width; the categorical axis stays a closed enum); `Cost = Time|Space|Energy` → a record (every cost has all three); and `\"WDS200T2X0E\"` → `NvmeDeviceCatalogRow \{ pcie_link: PcieLink \{ generation: Gen4, lane_count: 4 \}, form_factor: M2_2280, .. \}` (storage's rank/width: `lane_count` a cardinal `Int`, `PcieGeneration` a closed enum, per-lane bandwidth *derived* not stored — cited to the PCI Express authority in `extdeps/storage/types.dag` and surfaced through `product.compute_fabric`'s `StorageDevice.catalog`, parallel to the DRAM row above). (`GpuFacts.vendor`, once a bare `NonEmptyStr` where `CpuVendor` was a closed enum, is now grounded on the single `Vendor<Hardware>` authority — see §3.)"),
         ]),
       ]),
     ]),