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v4 T-4.9: model extdeps/languages/verilog.dag — HW concurrency as 5 behaviors (IN-B probe PASS) - #3177

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Summary

The IN-B mapping (member-by-member) lives in the modeling-notes "IN-B PROBE FINDING" section: module body ↦ Conj of parallel siblings; continuous assign ↦ Transform; always-block ↦ bounded Loop step + boundary-driven iteration (per node.dag A2 footnote); procedural statement sequence ↦ Bind; if/case ↦ Branch; signal declaration ↦ effect-typed value; module instance ↦ structural Conj child.

Test plan

  • v2-compiler compile --source-root src/v4 --target dag → 63 modules / 0 diagnostics
  • Every coproduct ≥2 variants carries the full 5-pattern Practice-4 ledger with the "five patterns attempted" lead-in (Connective / Behavior / NodeKind / EdgeLabel / EdgeDiscipline / FreeMonoid / Ordering / spice Component / ptx StateSpace precedent)
  • Scaffold-header Scope / Owns / Stress / Clear win lines preserved verbatim; staleness surfaced in Status, not silently rewritten (manager directive)
  • No per-target algebra inhabitance instance-values declared (D2 deferred)
  • No parse/emit function bodies declared (D1 Outcome deferred)
  • No new files; no new std/ concepts; no hand-Rust

🤖 Generated with Claude Code

…ehaviors (IN-B probe PASS)

IN-B probe RESULT: PASS — Verilog hardware concurrency models cleanly
under the existing five L1 behaviors with NO 6th `Concurrent` behavior
and NO core/pipeline change. The probe surfaces the structurally-
correct intra-vs-cross-program partition: intra-program HW concurrency
(parallel always-blocks / continuous assigns within one module) is the
Conj-of-parallel-siblings + Bind-chain-within-always shape, with per-
language effect-typing intrinsic to the wire/reg/vector signal type;
cross-program coordination (Endpoint/DeploymentUnit/messaging) is a
distinct concern owned by extdeps/coordination.dag (T-4.8).

Declares closed-Disj coproducts (each with full 5-pattern Practice-4
ledger — Fact-placement / Variant-is-data / Algebraic-form / Dimensional
/ Parameterized-family-Practice-7 per modeling-discipline.md §4):
PortDirection, NetType, VariableType, EdgeTrigger,
ProceduralAssignKind, PackingShape, ModuleItem. Conj records (no
ledger): VectorRange (🟡 scaffold), NetDeclaration, VariableDeclaration,
PortDeclaration, ParameterDeclaration, SensitivityItem,
ContinuousAssign, AlwaysBlock, InitialBlock, PortConnection,
ModuleInstance, VerilogModule, VerilogCost (🟡 scaffold).

DEFERRED with named-owner+trigger (do not author, do not improvise):
- emit/parse ops ride D1 Outcome<T> (Produced{value:T}|Rejected{...})
  when ratified in std/diagnostic.dag (v4 value-or-Diagnostic STOP
  surfaced by T-4.6 keen-wren-419).
- Bit-vector inhabitance (Semiring<UInt<N>> / OrderedRing<Int<N>>) rides
  pending D2 instance-value form (PR #3171's worker pushback precedent).
- Expression sub-grammar (RHS of assign, procedural-statement bodies,
  control-flow conditions) ride the T-4 LanguageModel bundle; verbatim
  String lexemes carry the textual surface in the interim (spice.dag
  SpiceValue.lexeme precedent).

Scaffold-header Consumes line preserved verbatim with surfaced staleness
(primitive.dag deleted PR #3152; coordination.dag is an unfilled scaffold
modeling cross-program coordination — a different concern from intra-
program HW concurrency). The systemic per-file Consumes reconciliation
is pending operator ratification (T-4 mgr synthesis msg_1fddb75c).

Verification: `v2-compiler compile --source-root src/v4 --target dag`
= 63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls

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Duplicate — dashboard-tracked PR is #3176 (same branch). Consolidating to that one.

@briansrls briansrls closed this May 16, 2026
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