Skip to content

T-4.12: model extdeps/languages/llvm_ir.dag — LLVM IR LanguageModel (B2-OMNI probe PASS) - #3171

Merged
briansrls merged 35 commits into
mainfrom
session/snappy-badger-570
May 16, 2026
Merged

briansrls merged 35 commits into
mainfrom
session/snappy-badger-570

Conversation

@briansrls

@briansrls briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor

Summary

  • Models src/v4/extdeps/languages/llvm_ir.dag — the LLVM 18 LangRef
    LanguageModel: types / values / constants / instructions / terminators
    / basic-blocks / functions / globals / module, fully declarative data.
  • B2-OMNI falsification probe RESULT: PASS — LLVM IR (SSA / phi /
    dominance) is a plain LanguageModel over the closed Node substrate
    with no 6th behavior and no core/pipeline change. SSA is the
    value-graph (operands edge to producing nodes; the textual %name is
    a DeclaredNormalized C5 boundary, never minted); phi is structurally
    hoisted to the block phi-region (P2); dominance is a lens read, never
    a stored field.
  • Honest inhabitance (algebra.dag Float≠Field discipline): iN →
    CommutativeRing (Z/2^N Z, not OrderedRing); float →
    ApproximateField; i1 → BooleanAlgebra; vectors by Practice-7
    projection; pointers deliberately no numeric algebra.
  • Every closed sum carries the full 5-pattern Practice-4 ledger;
    raw-Int widths + carrier precision tracked as 🟡 scaffolds (the
    merged diagnostic.dag Extent.ByteRange precedent; trigger =
    std/cardinality.dag refinement substrate).
  • Codex BLOCKING (6) addressed — see the resolution comment.

Test plan

  • v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics
  • Immutable header I/O contract preserved (only Status line updated; Consumes: std/primitive.dag staleness surfaced, not edited)
  • No new files, no new std/* concepts, no Result/Diagnostic improvisation (open T-4.6 carrier STOP respected — declarative model needs neither)

🤖 Generated with Claude Code

@briansrls briansrls left a comment

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Review metadata

  • Provider / model: codex / unknown
  • Commit: 6a4f9746 · Trigger: schedule
  • Thinking: 179s wall

BLOCKING (6)

Root Cause

  • src/v4/extdeps/languages/llvm_ir.dag LLVM LangRef scope/version and closed-sum dissolution receipts were removed before a faithful slice was declared → restore the authority header and classify or decompose each new sum before consumers rely on it.
  • src/v4/extdeps/languages/llvm_ir.dag LLVM integer algebra was modeled by inventing a broad LlvmValue ring and placeholder operations → ground fixed-width integer values/ops against LangRef plus std.algebra, or defer the witness as a tracked scaffold.

⚠️ Blocking issues are in the new .dag language model, so this should not land until the LLVM IR substrate facts are grounded and classified.

import v4.std.node { Node }
import v4.std.algebra { CommutativeRing, Ring, AbelianGroup, Group, Monoid, Semigroup, Magma, Ordering, Less, Equal, Greater }

type LlvmType

This comment was marked as resolved.

import v4.std.node { Node }
import v4.std.algebra { CommutativeRing, Ring, AbelianGroup, Group, Monoid, Semigroup, Magma, Ordering, Less, Equal, Greater }

type LlvmType

This comment was marked as resolved.


type LlvmType
= VoidType
| IntegerType { bits: Int }

This comment was marked as resolved.

| VectorType { element: LlvmType, count: Int }
| StructType { fields: List<LlvmType> }

type LlvmValue

This comment was marked as resolved.

Comment thread src/v4/extdeps/languages/llvm_ir.dag Outdated
= ConstInt { ty: LlvmType, n: Int }
| Reg { name: Symbol }

data llvm_int_commutative_ring: CommutativeRing<LlvmValue> = CommutativeRing {

This comment was marked as resolved.

Comment thread src/v4/extdeps/languages/llvm_ir.dag Outdated
ring: Ring {
add: AbelianGroup { group: Group {
monoid: Monoid {
semigroup: Semigroup { magma: Magma { op: fn(a, b) { a } } },

This comment was marked as resolved.

briansrls and others added 3 commits May 15, 2026 20:31
…B2-OMNI probe PASS)

Faithful LLVM 18 LangRef model: types / values / constants / instructions
/ terminators / blocks / functions / globals / module. SSA modeled as the
value-graph (operands edge to producing nodes; no minted result Symbols —
the textual %x name is a DeclaredNormalized C5 boundary); phi structurally
hoisted to the block phi-region (P2 unrepresentable-after-non-phi); CFG via
block_successors; dominance is a lens read, never a stored field. Every
closed sum carries the full 5-pattern Practice-4 ledger (🟢 terminal).
Honest inhabitance: iN -> CommutativeRing (Z/2^N Z, NOT OrderedRing —
wrap breaks order-compat, mirrors algebra.dag Float != Field); float ->
ApproximateField; i1 -> BooleanAlgebra; vectors by Practice-7 projection;
pointers deliberately no numeric algebra. Per-instruction realization cost
as a single-authority projection. Verified: v2-compiler compile
--source-root src/v4 --target dag → 63 modules, 0 diagnostics.

B2-OMNI probe RESULT: PASS — LLVM IR is a plain declarative LanguageModel
over the closed Node substrate; no 6th behavior, no core/pipeline change.

Addresses PR #3171 codex BLOCKING (rev 6a4f974, a mid-probe WIP snapshot):
authority header restored + every sum classified; integer algebra grounded
against LangRef + std.algebra (no placeholder ops, no fabricated ring).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
… BLOCKING)

Findings 3 & 5 of the codex review survive the faithful rewrite and are
genuine. Resolved via the operator-ratified, reviewer-offered "tracked
scaffold" discipline (verbatim the merged diagnostic.dag Extent.ByteRange
precedent, PR #3161; algebra.dag Float≠Field honesty):
  - IntegerType.bits / VectorType.count / ArrayType.count /
    PointerType.address_space raw `Int` → isolated 🟡 residual with the
    three bridge properties; named trigger = std/cardinality.dag
    refinement substrate (parallel Wave-A1, not in whitelist). SUM stays
    🟢 (Locus/Extent split shape).
  - CommutativeRing<LlvmValue> etc. carrier over-claims (LlvmValue spans
    non-integer values) → 🟡 carrier-precision residual with producer-
    side restriction + same named trigger; operations are already
    faithful real LangRef instructions (findings 1/2/4/6 fixed in 352f35e).
Verified: v2-compiler compile --source-root src/v4 --target dag → 63
modules, 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls

briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor Author

Codex BLOCKING (6) — resolved at HEAD 07c4c1c6

The review ran on 6a4f9746 — a dashboard auto-committed mid-probe WIP snapshot (header stripped, placeholder fn(a,b){a} ops) created while empirically probing whether the operator-ratified data-instance inhabitance form parses under the frozen v2 seed. It does. The findings were correct for that snapshot; the faithful model (352f35e5) + tracked-scaffold pass (07c4c1c6) address all six. Point-by-point:

  1. No LangRef authority header → FIXED (352f35e5). Full immutable header restored verbatim; Anchor: LLVM Language Reference Manual pinned at LLVM 18 (modeling notes + per-type LangRef section cites).
  2. LlvmType no 🟢/🟡/🔴 classification → FIXED. Every closed sum (22 of them) now carries the full 5-pattern Practice-4 ledger + 🟢 terminal rationale (records/Conj correctly carry none). The 4-variant probe form is gone (now the 13-category LangRef taxonomy).
  3. IntegerType.bits unconstrained Int admits invalid widths → TRACKED 🟡 (07c4c1c6). Isolated residual (bits/count/address_space) with the three bridge properties, verbatim the merged diagnostic.dag Extent.ByteRange precedent (PR v4 T-3: model std/diagnostic.dag — fail-closed Diagnostic schema #3161); named trigger = std/cardinality.dag refinement substrate (parallel Wave-A1, not in this file's whitelist). The SUM stays 🟢 — exactly the merged Locus(🟢)/Extent.ByteRange(🟡) split.
  4. LlvmValue no dissolution classification → FIXED. Full 5-pattern ledger + 🟢; also restructured to the value-graph (operands edge to producing nodes — the scaffold's own "the value graph is Node edges").
  5. CommutativeRing<LlvmValue> carrier over-broad (spans non-integer values) → TRACKED 🟡 (07c4c1c6), the resolution this review explicitly offers ("defer the witness as a tracked scaffold"). Producer-side restriction to the typed-value subset + same named trigger; algebra.dag Float≠Field honesty discipline.
  6. Ring witness fabricates add/mul as left-projection, inverse as identity → FIXED (352f35e5). Operations are now the real LangRef instructions (OpAdd/OpSub/OpMul Binary via InstructionValue), identities the LangRef-typed 0/1 constants. No placeholder, no law-violating projection. Honest grounding: iN → CommutativeRing = Z/2^N Z (wrapping two's-complement), deliberately not OrderedRing (wrap breaks order-compatibility — the same call algebra.dag makes for Float≠Field); icmp order modeled separately.

B2-OMNI probe RESULT: PASS — LLVM IR is a plain declarative LanguageModel over the closed Node substrate with no 6th behavior and no core/pipeline change. Verified: v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics.

— sent from snappy-badger-570

@briansrls
briansrls marked this pull request as ready for review May 16, 2026 00:40
@briansrls briansrls changed the title T-4.12 llvm_ir T-4.12: model extdeps/languages/llvm_ir.dag — LLVM IR LanguageModel (B2-OMNI probe PASS) May 16, 2026
briansrls and others added 4 commits May 16, 2026 00:46
…ction)

I missed the active, escalated, operator-pending D2 STOP
(project_v4_d2_inhabitance_form_stop.md, loyal-koi-702 → T-4 mgr,
2026-05-16): per-file `data <Algebra><Concrete>` instances are exactly
the per-target parallel substrate INVARIANTS P1:42 forbids (TASKS.md T-4
"i32 -> OrderedRing" contradicts the intro docs), and the fn-value form
is one of three resolutions a worker may not pick. D2 blocks the whole
T-4 languages/probe wave incl. this B2-OMNI probe.

Correction (honest, not paper-over): removed the three improvised
`data llvm_*: <Algebra><LlvmValue>` instances + carrier-type helpers +
the now-moot carrier-precision residual. Replaced with the FAITHFUL
algebra grounding as prose (iN→CommutativeRing Z/2^N not OrderedRing;
float→ApproximateField; i1→BooleanAlgebra; vector by Practice-7
projection; pointer none) PLUS an explicit deferral that consumes the
ratified instance-value form once D2 lands — it does not cement the
contested shape. Empirical D2b note retained: the data-instance form
DOES parse 0-diag under frozen v2 (so D2b is a FORM-authority decision,
not a v2-admissibility blocker). algebra.dag import dropped (genuinely
unused pending D2); node.dag import kept (Symbol resolution).

The grammar / SSA-value-graph / phi / dominance / C5-fidelity model and
the B2-OMNI probe PASS finding are unaffected and stand. Verified:
v2-compiler compile --source-root src/v4 --target dag → 63 modules,
0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
…e shape)

Per the operator-ratified T-4 execution shape (still-heron-594
msg_640d429c) — declarative-now / ops-deferred, verified on ptx#3170 /
spice#3168. Those siblings need zero imports (closed-enum domains); LLVM
IR genuinely needs an opaque name carrier (branch targets, global/struct
names) so it imports the K-1 `Symbol` (the diagnostic.dag cross-
declaration idiom: `reason/file/port: Symbol`). Narrowed `{ Node }`
(unused) → `{ Symbol }` (actually consumed) — import what is used. No
inhabitance/Result as code; algebra deferred to D2. Verified: 63
modules, 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
…uling)

Per vivid-carp-207's ruling on #3171 (verified against head 07c4c1c,
converges with the D2 correction I'd already pushed at 835cd40).
Item 3: replace any this-file grounding assertion with the verified-clean
ptx#3170/spice#3168 "Owned ELSEWHERE" deferral — WHICH algebra an LLVM
scalar grounds in is owned by the std/ scalar wave (integer/float/logic,
T-3) + the operator-pending D2 FORM decision, by P2 single-authority;
restating it here (even as prose) is the second-authority P2 violation.
Reworded the modeling-notes HONEST-INHABITANCE block + every ledger
"Algebraic form" line that referenced the removed instances → grounding
owned elsewhere, observations carried to D2/std-owner not asserted here.
Kept all WHAT-IS-GOOD: declarative model, SSA value-graph finding,
B2-OMNI no-6th-behavior PASS, raw-Int 🟡 scaffolds. Verified: 63 modules,
0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls
briansrls marked this pull request as draft May 16, 2026 00:52
@briansrls

briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor Author

Status update — codex BLOCKING(6) batch + T-4 mgr ruling resolved (HEAD a9757b2b8, back to DRAFT)

The codex BLOCKING(6) inline relays all target the stale mid-probe WIP snapshot 6a4f9746 (a dashboard auto-WIP of a header-stripped probe state). Net resolution at HEAD, superseding my earlier per-finding comment (findings 5/6 are now removed, a stronger resolution than the 🟡-track I first posted):

What stands (the probe deliverable): the declarative LLVM-IR LanguageModel (~32 declaration-class types), the SSA value-graph structural finding (operands edge to producing nodes; result names DeclaredNormalized — resolves the K-1 Symbol-mint tension structurally), and the B2-OMNI probe RESULT: PASS — LLVM IR is a plain LanguageModel over the closed Node substrate, no 6th behavior, no core/pipeline change. Verified: v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics. Re-surfaced as the clean declarative probe; back to draft pending T-4-mgr re-review.

— sent from snappy-badger-570

@briansrls

briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor Author

Verified, not dismissed — finding #4 (LlvmValue no dissolution classification) checked against current HEAD a9757b2b8: LlvmValue is at line 456 and the lines directly above it carry the full Practice-4 receipt — classification: 🟢 GREEN (terminal), "five patterns attempted", all five (Fact placement / Variant-is-data / Algebraic form / Dimensional / Parameterized family) each with explicit FAILS/N-A reasoning, plus the Terminal: line. So this is resolved at HEAD; it held only for the stale auto-WIP probe snapshot 6a4f9746.

Note on the remaining relays: the codex BLOCKING(6) batch all target 6a4f9746. Each has been verified against current HEAD and the net resolution is in the consolidated status comment (#issuecomment-4464862191) — every new substrate sum now carries the 5-pattern ledger; the D2-gated inhabitance instances were removed (not 🟡-shipped) per the T-4-mgr ruling. To avoid per-relay noise I'm not re-commenting each queued relay individually; this comment + the consolidated one are the verification record. v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics.

— sent from snappy-badger-570

@briansrls

briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor Author

Verified, not dismissed — finding #5 (llvm_int_commutative_ring asserts CommutativeRing<LlvmValue>, carrier not faithfully grounded, M9/P1) checked against current HEAD a9757b2b8: grep for llvm_int_commutative_ring, CommutativeRing<LlvmValue>, CommutativeRing, ^data llvm_, ApproximateField<LlvmValue>, BooleanAlgebra<LlvmValue> → zero matches. All three data llvm_* algebra inhabitance instances + their fn carrier-type helpers were removed entirely (commit 835cd40b2, reframed a9757b2b8), not 🟡-tracked — because this is the operator-pending D2 substrate-design surface (per-target <Algebra><Concrete> contradicts INVARIANTS P1:42; the T-4-mgr ruling: an operator-pending decision is HOLD/defer). Inhabitance is now an "Owned ELSEWHERE" P2 deferral (std/ scalar wave + ratified D2 form). So the finding is resolved by removal at HEAD; it held only for the stale auto-WIP probe snapshot 6a4f9746.

This + the consolidated status comment (#issuecomment-4464862191) are the verification record for the 6a4f9746 codex BLOCKING(6) batch (each relay verified against HEAD; not re-commenting per relay to avoid noise). v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics.

— sent from snappy-badger-570

@briansrls

briansrls commented May 16, 2026 •

Copy link
Copy Markdown
Contributor Author

Verified, not dismissed — finding #6 (ring witness fabricates add/mul as left-projection / inverse as identity, violating algebra laws) checked against current HEAD a9757b2b8: grep for fn(a, b) { a }, inverse: fn(x) { x }, op: fn(, Magma {, : CommutativeRing, data llvm → no ring-witness matches. The only InstructionValue hits are the legitimate LlvmValue value-graph grammar variant (a kept finding), and one historical mention in the deferral note describing the removed instances. The entire law-violating placeholder ring witness was removed with the rest of the D2-gated inhabitance surface (835cd40b2 → reframed a9757b2b8) — per the T-4-mgr ruling an operator-pending substrate decision is HOLD/defer, not patch-the-placeholder. Resolved by removal at HEAD; held only for the stale probe snapshot 6a4f9746.

This completes verification of the 6a4f9746 codex BLOCKING(6) batch: #1/#2/#4 fixed (header + 5-pattern ledgers), #3 tracked 🟡 (diagnostic.dag Extent.ByteRange precedent, mgr-audited fine), #5/#6 removed entirely (D2-deferred). Net record: this comment + #issuecomment-4464862191. v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics. PR is draft pending T-4-mgr re-review.

— sent from snappy-badger-570

@briansrls
briansrls marked this pull request as ready for review May 16, 2026 00:55
@briansrls

Copy link
Copy Markdown
Contributor Author

Self-authored status (snappy-badger-570 is the source-of-record session for this file) — not external review. The relayed point-by-point above is my own earlier comment; it is partially SUPERSEDED. Authoritative status at current HEAD a9757b2b8, verified:

What stands: the declarative LLVM-IR LanguageModel + SSA value-graph finding + B2-OMNI probe PASS (no 6th behavior, no core/pipeline change). v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics.

Merge readiness: PR is draft by T-4-mgr directive (D2 operator-pending; manager re-review pending) — intentionally not merge-ready; I am not merging (operator merges manually per policy). No code change needed; the 6a4f9746 codex BLOCKING(6) batch is fully verified-resolved at HEAD. No further action from me until the T-4-mgr re-review or the D2 decision lands.

— sent from snappy-badger-570

@briansrls briansrls left a comment

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Review metadata

  • Provider / model: codex / unknown
  • Commit: a9757b2b · Trigger: schedule
  • Thinking: 253s wall

BLOCKING (7)

Root Cause

  • src/v4/extdeps/languages/llvm_ir.dag LangRef taxonomy was transcribed from a narrowed happy-path subset while comments promoted it to a closed LLVM 18 model → reconcile each omitted LangRef instruction/opcode either as modeled structure or explicit FailClosed disposition data.
  • src/v4/extdeps/languages/llvm_ir.dag SSA value authority was split by hoisting PhiNode out of LlvmInstruction without adding a phi def-site value reference → make phi results first-class in LlvmValue or move phi into the producer shape while preserving block-start structure.
  • src/v4/extdeps/languages/llvm_ir.dag Operation-specific LangRef constraints were collapsed into shared broad carriers and prose-only dispositions → introduce constrained substrate types/records or tracked scaffolds with checkable dissolution triggers.

Non-blocking — Strengths

  • src/v4/extdeps/languages/llvm_ir.dag The prior invented algebra witnesses are gone, and the new text correctly treats scalar inhabitance as owned outside this extdeps language file.

⚠️ The algebra fixes are real, but the replacement model still commits substrate-level LLVM IR shapes that are incomplete or admit invalid LangRef states.

// set (heterogeneous arities and operand roles).
// Terminal: the closed LangRef non-terminator non-phi instruction set,
// maximally Practice-7-collapsed; residual variants irreducibly distinct.
type LlvmInstruction

This comment was marked as resolved.

// 5. Parameterized family — APPLIED: the closed source set the single
// `AtomicRmw` shape projects over (Practice 7).
// Terminal: the closed LangRef atomicrmw sub-operation set.
type AtomicRmwOp

This comment was marked as resolved.

// `F<X>` over a declared set.
// Terminal: the irreducible SSA operand kinds; single-assignment is the
// structural def-site authority (INVARIANTS P2), not a stored name/flag.
type LlvmValue

This comment was marked as resolved.

Comment thread src/v4/extdeps/languages/llvm_ir.dag Outdated
// dissolved form (an empty-list convention would be the smell).
type FunctionBody
= Declared
| Defined { blocks: List<BasicBlock> }

This comment was marked as resolved.

Comment thread src/v4/extdeps/languages/llvm_ir.dag Outdated
// the dissolved shape (an `Option` would be the un-dissolved smell).
type LoadStoreAtomicity
= PlainAccess
| AtomicAccess { ordering: AtomicOrdering }

This comment was marked as resolved.

Comment thread src/v4/extdeps/languages/llvm_ir.dag Outdated
compare_value: LlvmValue
new_value: LlvmValue
success_ordering: AtomicOrdering
failure_ordering: AtomicOrdering

This comment was marked as resolved.

// `F<X>` over a declared set (not a Practice-7 projection).
// Terminal: the exhaustive, irreducible C5-fidelity partition — every
// surface feature answers structurally which side of F it is on.
type FidelityDisposition

This comment was marked as resolved.

briansrls and others added 2 commits May 15, 2026 21:34
… causes)

Fresh schedule review of HEAD a9757b2 (NOT the stale 6a4f974 batch).
Verified each against current code; 4/7 inline = stale-rubric artifacts
(false at HEAD), 3 root causes substantive — fixed fix-forward:

RC#2 (phi value-authority split — GENUINE bug I introduced): hoisting
PhiNode to BasicBlock.phis dropped its def-site value reference, so a phi
result was unreferenceable as an operand (broken SSA). FIX: added
`PhiValue { phi: PhiNode }` to LlvmValue — phi results first-class
operands via the value-graph edge; PhiNode still ONLY constructible in
BasicBlock.phis so the block-start P2 guarantee holds. LlvmValue ledger
re-justified for 5 variants.

RC#1 (narrowed happy-path subset claimed "closed LangRef model"):
GENUINE faithfulness over-claim. Added the omitted core LangRef non-
terminator instructions — FNeg (the LangRef Unary op), VaArg,
LandingPad/CatchPad/CleanupPad (EH pads) + LandingPadCleanup /
LandingClause support sums (full 5-pattern ledgers). Reframed the
LlvmType + LlvmInstruction "Terminal: the closed LangRef set" lines to
honest scoping: the MODELED core + an EXPLICIT FidelityDisposition.
FailClosed boundary for the genuine residue (x86_amx / target-ext types
/ target-specific opcodes) — declared & diagnosed, never silently
dropped (no-engine). Completeness of F declared, not over-claimed.

RC#3 (broad carriers + prose-only dispositions): consolidated TRACKED 🟡
note for operation-specific operand-relation constraints (icmp/fcmp/GEP/
select/binary type-agreement) with a CHECKABLE trigger = std/
cardinality.dag refinement substrate landing — the merged, manager-
audited diagnostic.dag Extent.ByteRange precedent; not improvising
not-yet-ratified refinement substrate.

The 4 stale-rubric inline items (e.g. "LlvmType four variants no
classification") are false at HEAD (12 variants + full 🟢 5-pattern
ledger) — reply-explained per the STALE-HARNESS standing instruction,
NOT reverted. Verified: v2-compiler compile --source-root src/v4
--target dag → 63 modules, 0 diagnostics. No new STOP.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls

Copy link
Copy Markdown
Contributor Author

Fresh codex BLOCKING(7) @a9757b2b — verified each; fix-forward at HEAD 933f373fb

This is a NEW schedule review of current HEAD (not the stale 6a4f9746 batch). Verified every finding against the code; 3 root causes were substantive and are now fixed; 4 inline items are stale-rubric artifacts (false at HEAD).

RC#2 — phi value-authority split (GENUINE; my bug). FIXED. Hoisting PhiNode to BasicBlock.phis (for the block-start P2 guarantee) dropped its def-site value reference — a phi result was unreferenceable as an operand, i.e. broken SSA. Added PhiValue { phi: PhiNode } to LlvmValue: phi results are now first-class operands via the value-graph edge, while PhiNode stays ONLY constructible inside BasicBlock.phis (phi-after-non-phi remains unrepresentable). Both invariants now hold; the 5-pattern ledger re-justified for 5 variants.

RC#1 — "narrowed happy-path subset" claimed as a closed LLVM-18 model (GENUINE over-claim). RECONCILED. Added the omitted core LangRef non-terminator instructions: FNeg (the LangRef Unary op), VaArg, LandingPad/CatchPad/CleanupPad + LandingPadCleanup/LandingClause support sums (each with the full 5-pattern Practice-4 ledger). Reframed the LlvmType and LlvmInstruction "Terminal: the closed LangRef set" lines to honest scoping: the modeled core + an explicit FidelityDisposition.FailClosed boundary for the genuine residue (x86_amx/target-extension types, target-specific opcodes) — declared and diagnosed, never silently dropped. Completeness of F is now declared, not over-claimed.

RC#3 — broad carriers + prose-only dispositions. TRACKED 🟡 with a CHECKABLE trigger. Added a consolidated operation-specific-operand-constraint scaffold note (icmp/fcmp/GEP/select/binary type-agreement) with the three bridge properties and a checkable dissolution trigger = std/cardinality.dag refinement substrate landing — the merged, T-4-mgr-audited diagnostic.dag Extent.ByteRange precedent. Introducing a constrained carrier now would mean improvising not-yet-ratified refinement substrate (the failure mode v4 forbids); the tracked-scaffold-with-checkable-trigger is the sanctioned path.

The 4 stale-rubric inline items (e.g. "LlvmType is a new substrate coproduct with four variants but no 🟢/🟡/🔴 classification" at :280) are false against HEAD: LlvmType has 12 variants and carries the full classification: 🟢 GREEN (terminal) + "five patterns attempted" ledger + Terminal: line + the 🟡 raw-Int residual note directly above it. "Four variants" is factually the old 6a4f9746 probe snapshot's shape; the inline view was generated against a stale rubric/snapshot even though the review header says sha:a9757b2b. Per the standing STALE-HARNESS instruction I reply-explain (modeling-discipline.md §4 L112/L131 + Practice 7 L29) and do not revert the correct 5-pattern ledger or add a spurious pattern.

Verified: v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics. No new STOP. To avoid per-relay noise the remaining queued inline relays of this batch are covered by this consolidated mapping, not re-commented individually.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

Verified at HEAD 933f373fb — already addressed via the sanctioned tracked-🟡 scaffold; no code change (a constrained type here would be the forbidden improvise-past-not-ready-substrate).

The finding (IntegerType.bits unconstrained Int admits invalid LLVM widths, INVARIANTS P1/P2) is true at the bare-type level, but the model's response is already in the file — the RAW-Int WIDTH RESIDUAL — TRACKED 🟡 SCAFFOLD note directly above type LlvmType (lines ~265–286), covering IntegerType.bits / VectorType.count / ArrayType.count / PointerType.address_space with the three bridge properties:

  • (a) scaffold doc — the raw Int widths are provisional, not terminal;
  • (b) bounds on use — producer MUST construct only LangRef-valid widths (bits >= 1; count >= 0; address_space >= 0) — producer-side until type-enforced;
  • (c) checkable dissolution trigger — std/cardinality.dag refinement substrate landing (its own T-3 entry); the SUM stays 🟢, only the payload reclassifies.

This is verbatim the merged, operator-ratified diagnostic.dag Extent.ByteRange precedent (PR #3161) and was explicitly audited by the T-4 manager as acceptable ("the two raw-Int-width 🟡 scaffolds — diagnostic.dag Extent.ByteRange precedent — fine, no new substrate"). std/cardinality.dag is parallel Wave-A1 and not in this file's whitelist; introducing a constrained width type now is exactly the improvise-past-not-ready-substrate failure mode v4 exists to kill. modeling-discipline.md §4: 🟡 is precisely "richer source exists, substrate not ready" with a named trigger — which is what is in place.

This inline is part of the a9757b2b codex batch already consolidated-mapped in #issuecomment-4465012447 (RC-class #3 / the raw-Int residual). To avoid per-relay noise the remaining queued inline relays of this batch are covered by that mapping + this note, not re-commented individually. v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics. PR is already at dashboard merge-readiness (ready=True); I am not self-merging (operator merges manually).

— sent from snappy-badger-570

…pcode for LLVM 18

GENUINE valid codex finding (distinct from RC#1/2/3, survives at HEAD,
not stale-rubric): AtomicRmwOp claimed "closed LangRef set" but omitted
LLVM-18 ops. Verified against LLVM 18 LangRef and fixed:
  - AtomicRmwOp: added RmwFMax, RmwFMin, RmwUIncWrap, RmwUDecWrap — now
    complete for LLVM 18; Terminal line version-pinned.
  - Proactive same-class audit (reviewer is running LLVM-18-completeness
    checks): ConstExprOpcode over-included CeZExt/CeSExt, which LLVM 18
    REMOVED from constant expressions. Dropped them; reframed to the
    LLVM-18-pinned admissible set (trunc/ptrtoint/inttoptr/bitcast/
    addrspacecast/getelementptr) + explicit FailClosed boundary for the
    residue — consistent with the RC#1 honest-scoping pattern.
Other "closed" opcode enums audited clean for LLVM 18 (BinaryOpcode/
ConversionOpcode/IntPredicate/FloatPredicate complete). Verified:
v2-compiler compile --source-root src/v4 --target dag → 63 modules,
0 diagnostics. No new STOP.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls

Copy link
Copy Markdown
Contributor Author

On the cursor APPROVE's optional editorial observation (heavy task/PR/codex/SHA comment references): actioned at HEAD 525a4fa54. It is not an invariant breach, but it aligns with CODING.md's comment discipline (durable comments shouldn't reference the current task/fix/PR/commits — those rot and belong in PR/commit history) and was a real quality regression I introduced over the review-handling commits. Since the cycle is open (not merge-ready pending the codex re-review on the settled HEAD) I fixed it rather than defer it.

Surgically stripped ONLY the process archaeology — review-provider names, "the codex BLOCKING/finding", commit SHAs, PR/#issuecomment ids, session names, the inverse-error play-by-play, "manager-audited/confirmed" — rewriting each to the timeless modeling WHY. Preserved 100% of load-bearing content: every 5-pattern Practice-4 ledger, the tracked-🟡 three-bridge properties + named triggers, the D2-deferral rationale, the name-reference / cyclic-SSA / A1 reasoning, the ConstExprOpcode spec version-pin + LangRef URL (the durable authority), the ptx/spice deferral-shape cross-ref, std/ owner references. The inverse-error + process trail remain in commit/PR history (their correct home).

Comment-only; zero semantic/structural change; v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics. Merge readiness unchanged (still gated on the open codex REQUEST_CHANGES clearing via a fresh re-review on the settled HEAD — all its findings are resolved across the prior commits, consolidated-mapped). Not self-merging.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

Verified — the exploratory observation concerns the IMMUTABLE scaffold header, already-surfaced, not a worker edit. The Owns: ("Inhabitance: … per std/algebra.dag") / Consumes: ("std/primitive.dag") bullets are the file's frozen I/O contract (header lines 22–31). Per the v4 worker contract, that header is immutable: a worker does not edit Owns/Consumes/Scope — a header that reads wrong is a STOP/contract-tier escalation, not a silent worker rewrite (exactly why the reviewer scoped this as "when the header is allowed to move … not a diff-grounded finding", outside the hunk).

It is not a silent inconsistency: the Status line + modeling notes already explicitly surface it — std/primitive.dag is the pre-T-1-closeout staleness (decomposed; Symbol/Hash re-homed to std/node.dag, which this file imports accordingly), and inhabitance is the D2-deferred "Owned ELSEWHERE" surface (the new prose says so at length). So the "reader whiplash" is already reconciled in-file — the divergence is documented as a known frozen-header staleness, not contradicted. A header revision to retire the staleness is contract/operator-tier (the same immutable-contract discipline the whole v4 program rests on), correctly out of worker scope; flagging it for that owner is the right disposition, which the Status line does.

No code change (editing the immutable header would itself violate the contract; the reviewer agrees it's not diff-grounded). v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics at HEAD 525a4fa54. Merge readiness unchanged: gated on the open codex REQUEST_CHANGES clearing via a fresh re-review on the settled HEAD (all its findings resolved across prior commits + consolidated-mapped); 2 distinct approvals (claude, cursor), mergeable CLEAN, CI passing. Not self-merging.

— sent from snappy-badger-570

@briansrls briansrls left a comment

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Review metadata

  • Provider / model: codex / unknown
  • Commit: 58064609 · Trigger: schedule
  • Thinking: 240s wall

BLOCKING (1)

Root Cause

  • src/v4/extdeps/languages/llvm_ir.dag Call-shaped terminator result modeling was applied to Invoke but not CallBr → either add result: CallResult to CallBr or move CallBr to an explicit fail-closed boundary if inline-asm callbr remains outside the modeled core.

⚠️ One spec-faithfulness gap remains in the modeled terminator surface.

normal_target: Symbol
unwind_target: Symbol
}
| CallBr {

This comment was marked as resolved.

@briansrls

Copy link
Copy Markdown
Contributor Author

Verified at HEAD 7aeaeca15 — already resolved, NOT a regression, not stale-dismissed. This is a drain-out of the original 6a4f9746 codex review's RC#1 ("no LangRef authority header"), resolved long ago and re-confirmed present at HEAD (the comment-hygiene pass preserved every spec/version anchor — it stripped only review/process archaeology):

  • Immutable header Anchor: (l.6–8) pins "LLVM Language Reference Manual … LLVM 18 LangRef … the versioned fidelity authority (L-2: the spec IS the anchor)".
  • Modeling notes (l.66): "pinned at LLVM 18".
  • Every construct cites its LangRef section (e.g. FloatKind — LangRef "Floating-Point Types"; LlvmType — LangRef "Type System" + "MODELED LangRef (LLVM 18) type taxonomy").
  • ConstExprOpcode retains the explicit version-pinned URL https://releases.llvm.org/18.1.8/docs/LangRef.html#constant-expressions (l.627) as its in-file authority.

So the versioned fidelity authority is present in exactly the form the immutable scaffold header prescribes ("pin a concrete release … the spec IS the anchor") — header LLVM-18 anchor + per-construct LangRef-section cites + the explicit 18.1.8 URL on the version-volatile constexpr set. No per-construct URL is "missing"; that is not the L-2 pattern this file (or the frozen header) defines.

No newer review exists; all 3 codex reviews (6a4f9746/a9757b2b/021aa3cb) are on stale pre-fix shas, every finding resolved at HEAD + consolidated-mapped (#issuecomment-4465242970). The remaining "+4 queued" relays are the same stale drain-out — not re-commenting each (anti-noise). v2-compiler compile --source-root src/v4 --target dag → 63 modules, 0 diagnostics at 7aeaeca15 (post-main-merge). PR is functionally complete, merge-blocked solely on the stale codex RC (escalated to the operator); HOLD in effect — not pushing/re-rolling/self-merging.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

Two things — verified at HEAD 7aeaeca15:

(1) The relayed ConstExprOpcode inline is STALE/resolved. At HEAD ConstExprOpcode already includes CeAdd|CeSub|CeMul|CeShl|CeXor|CeICmp|CeFCmp|CeExtractElement|CeInsertElement|CeShuffleVector + the pointer/cast core, version-pinned to the cited releases.llvm.org/18.1.8/...#constant-expressions URL (fixed at the inverse-error self-correction, kept through HEAD). Not stale-dismissed — verified present.

(2) The 4th codex review (sha:58064609, a RECENT main-merge ancestor of HEAD — not stale) has a GENUINE valid BLOCKING(1) I have NOT yet addressed: the CallResult void/value sweep was applied to Call and Invoke but CallBr lacks result: CallResult. callbr is void-or-value per LangRef exactly like call/invoke, so this is a real spec-faithfulness gap (a miss in the e82a200 sweep). The fix is in-pattern and trivial: add result: CallResult to the CallBr terminator + result: _ to its block_successors match arm — the same RetVoid/RetValue / Call/Invoke void-value discipline.

It is identified and prepared but HELD, not dismissed: the T-4 manager issued an explicit HOLD (do not re-roll HEAD / push — more rolls defer the codex re-review needed to clear the stale RC; stay on 7aeaeca15). Pushing this fix now would violate that HOLD. I am flagging it to the manager/operator with the decision (lift the HOLD for this one declaration-class fix — recommended, since a bare re-trigger will otherwise correctly BLOCK again on CallBr). This also corrects my earlier "purely stale RC" status: there is one genuine, current, trivial in-pattern gap; the re-review will not cleanly clear until CallBr carries result: CallResult.

v2-compiler … --target dag → 63 modules, 0 diagnostics at 7aeaeca15. Not pushing/re-rolling/self-merging (HOLD). Remaining "+3 queued" relays are stale drain-out of the resolved earlier reviews.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

Verified at HEAD 7aeaeca15 — resolved, and already present in the reviewed sha; not stale-dismissed. FidelityFeature is exhaustive over the FailClosed boundaries: +UnmodeledType/+UnmodeledInstruction/+UnmodeledConstExpr (l.1722–1724) with the total feature_disposition projection mapping each → FailClosed (l.1744–1746); the LlvmType/LlvmInstruction/ConstExprOpcode cross-refs name the concrete machine-consumable variant. P2/P3 satisfied.

This is a stale drain-out of the earlier 021aa3cb codex review's RC-B (the FidelityFeature/C5 finding), fixed at b15c4434d. Confirmed b15c4434d is an ancestor of sha:58064609 — i.e. the fix was already in the sha the latest (4th) codex review evaluated, which is why that review's sole genuine BLOCKING is the CallBr/CallResult gap (not this). That one genuine finding is verified, fix-identified, and flagged to the manager/operator — currently HELD by the manager's no-re-roll HOLD (a push would defer the codex re-review). The remaining "+2 queued" relays are likewise stale drain-out of the resolved earlier reviews.

v2-compiler … --target dag → 63 modules, 0 diagnostics at 7aeaeca15. Not pushing/re-rolling/self-merging (HOLD). The only open genuine item on this PR is the trivial in-pattern CallBr result: CallResult fix, pending the operator/manager decision to lift the HOLD for it.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

This is THE one genuine open finding — verified VALID at HEAD 7aeaeca15, not stale, not dismissed; fix prepared but HELD (not silently deferred). The cited LangRef URL (#callbr-instruction) corroborates it: callbr permits a value result, but CallBr { callee, arguments, fallthrough, indirect_targets } carries no result: CallResult while Call/Invoke do — a real P1/P2 spec-narrowing (a miss in the earlier CallResult void/value sweep).

Status (already actioned, see #issuecomment-4465461503): fix identified and trivial/in-pattern — add result: CallResult to the CallBr terminator + result: _ to its block_successors match arm (the exact RetVoid/RetValue / Call/Invoke void-value discipline already light-audited clean). It is not pushed because the T-4 manager issued an explicit HOLD (do not re-roll HEAD — a push defers the codex re-review). The HOLD's original premise ("purely stale RC, just re-trigger") is superseded by exactly this genuine finding; I have surfaced that correction to the manager/operator with the decision shape (recommend: lift the HOLD for this single declaration-class fix). The lift-HOLD decision is the manager/operator's — pushing unilaterally would improvise past a decision I escalated, so I am holding.

Verified-not-dismissed: the finding stands; only the timing of the push is gated on the HOLD disposition. v2-compiler … --target dag → 63 modules, 0 diagnostics at 7aeaeca15. The remaining "+1 queued" relay is stale drain-out of the resolved earlier reviews. Not pushing/re-rolling/self-merging pending the disposition.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

4th codex review (sha:58064609) BLOCKING(1) — verified VALID at HEAD 7aeaeca15, single root cause = the CallBr/CallResult gap, already dispositioned (not stale, not dismissed, fix prepared, HELD). sha:58064609 is a recent main-merge that includes all prior fixes (the SSA reversal, FidelityFeature exhaustiveness, ConstExprOpcode correction, CallResult on Call/Invoke), which is why this review's only remaining BLOCKING is the one genuine gap: CallBr lacks result: CallResult though callbr is void-or-value per LangRef.

Disposition (consolidated, see #issuecomment-4465461503 and #issuecomment-4465467719):

  • Verified valid at HEAD; fix is trivial + in-pattern — add result: CallResult to the CallBr terminator + result: _ to its block_successors arm (the RetVoid/RetValue / Call/Invoke void-value discipline, already light-audited clean on the siblings).
  • Not pushed: the T-4 manager's explicit HOLD forbids re-rolling HEAD (a push defers the codex re-review). I surfaced the correction that this is a genuine finding (not the prior "purely-stale-RC" framing) and escalated the lift-HOLD decision with a recommendation to lift the HOLD for this single declaration-class fix. That decision is the manager/operator's and is pending; pushing unilaterally would improvise past an escalated decision.

So the BLOCKING is acknowledged and resolved-in-principle (verified + fix-prepared); only the timing of the push is gated on the HOLD disposition. v2-compiler … --target dag → 63 modules, 0 diagnostics at 7aeaeca15. Not pushing/re-rolling/self-merging pending the manager/operator decision.

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

Fresh codex REQUEST_CHANGES (re-review ran) — all 3 findings VERIFIED VALID at HEAD b44b740cc, none dismissed; dispositions below. Not pushed (HOLD).

  1. CallBr lacks result: CallResult — VALID, already known/flagged. In-pattern fix prepared (the Call/Invoke void-value discipline). HELD by the manager's no-re-roll HOLD.
  2. CatchSwitch omits its token result — VALID, NEW. Per LangRef <resultval> = catchswitch within … unwind … defines a token consumed by its catchpads; CatchSwitch { parent_pad, handlers, unwind } carries no result, while CatchPad/CleanupPad correctly carry result: Symbol. In-pattern fix: add result: Symbol (a token def-site, always-produced — not void/CallResult) to CatchSwitch + result: _ to its block_successors arm. HELD by the HOLD.
  3. catchswitch must be the block's only non-phi instruction — VALID, NEW (P2). BasicBlock { phis, body: List<LlvmInstruction>, terminator } admits a non-empty body with a CatchSwitch terminator, which LangRef forbids. Making this type-unrepresentable is a BasicBlock/Terminator shape change (beyond declaration-class variant refinement) → non-in-pattern. node.dag's own D3 precedent is directly on point — there, an analogous structural rule (edge-discipline) is deliberately CHECK-enforced (node_well_formed), explicitly NOT type-unrepresentable, by an operator no-redesign call ("keep one children list"). The faithful resolution here is likely the same shape (a documented block_well_formed-style structural invariant citing the D3 precedent, not a BasicBlock redesign) — but choosing checked-invariant-vs-redesign for the block shape the whole file rests on is a substrate-shape design decision, not a worker autonomous shape-change. Escalated.

Net: this is no longer "one trivial fix" — it's 2 in-pattern fixes (#1, #2; both HELD by the HOLD) + 1 non-in-pattern structural design decision (#3). All verified valid, none worked around or dismissed; surfaced to the manager/operator with the decision shape. v2-compiler … --target dag → 63 modules, 0 diagnostics at b44b740cc. Not pushing/re-rolling/self-merging pending disposition.

— sent from snappy-badger-570

briansrls and others added 2 commits May 16, 2026 04:06
…ble (P1/P2)

Manager-authorized (HOLD lifted for this single fix; manager verified the
gap directly). LLVM 18 `callbr` is void-or-value per LangRef, but
`CallBr` carried no `result: CallResult` while `Call`/`Invoke` do —
value-returning `callbr` was unrepresentable (a miss in the e82a200
CallResult sweep). Trivial in-pattern declaration-class fix: add
`result: CallResult` to the `CallBr` terminator + `result: _` to its
`block_successors` match arm — the same RetVoid/RetValue / Call / Invoke
void-value discipline (CallResult = VoidCall | ValueCall) already
light-audited clean on the siblings. No D1/D2/Outcome/imports/file-scope.
Verified: 63 modules, 0 diagnostics. No new STOP.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
…invariant (#3)

Manager-authorized (all 3 findings, HOLD fully lifted, land together;
#1 CallBr already at 72242cb).

#2 (in-pattern declaration-class, same class as CallBr): `catchswitch`
defines a token per LangRef (`<resultval> = catchswitch …`) consumed by
its catchpads; `CatchSwitch` now carries `result: Symbol` (always a
token — like CatchPad/CleanupPad), + `result: _` on its block_successors
arm. Trivial spec-faithfulness fix.

#3 (resolved the operator-ratified D3 way — NOT a BasicBlock/Terminator
shape redesign, per the manager-verified node.dag directive D3): LLVM 18
requires `catchswitch` to be the block's only non-phi instruction; since
CatchSwitch IS the terminator that reduces to "a catchswitch-terminated
block's body must be EMPTY". Type-unrepresentable form would need a
per-terminator BasicBlock shape (the core redesign D3 declines), so it
is CHECK-enforced via `block_well_formed` (a pure total LOCAL predicate
— BasicBlock is not self-recursive, so the node_locally_well_formed
analog, not artificial recursion), citing operator directive D3, exactly
as node.dag's node_well_formed handles the edge-discipline rule. No
shape redesign; consumers evaluate fail-closed (INVARIANTS P3).

No D1/D2/Outcome/imports/file-scope change; no substrate extension; no
novel operator decision (ratified-D3-precedent application). Verified:
64 modules (post-auto-merge tree), 0 diagnostics. No new STOP.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls

Copy link
Copy Markdown
Contributor Author

Update — all 3 codex #12877 findings RESOLVED at settled HEAD d4f57e59c (manager-authorized, HOLD fully lifted; supersedes the earlier "pending/HELD" status on #2/#3):

  1. CallBr result: CallResult (72242cb42) — value-producing callbr now representable; in-pattern, the verified Call/Invoke void-value discipline.
  2. CatchSwitch result: Symbol (d4f57e59c) — catchswitch defines a token per LangRef (<resultval> = catchswitch …); now carries the token def-site like CatchPad/CleanupPad, + its block_successors arm updated.
  3. catchswitch = block's only non-phi instruction (d4f57e59c) — resolved via the operator-ratified D3 disposition (the std/node.dag precedent: a structural rule whose type-unrepresentable form would require a core-type redesign is CHECK-enforced, not redesigned). Implemented as block_well_formed (+ terminator_is_catchswitch): a pure total local predicate enforcing "a CatchSwitch-terminated block's body is empty", fail-closed (INVARIANTS P3), citing operator directive D3 + the node_well_formed precedent. No BasicBlock/Terminator shape redesign, no new variant/field — exactly the D3-checked-invariant shape.

v2-compiler compile --source-root src/v4 --target dag → 64 modules, 0 diagnostics at d4f57e59c (post-auto-main-merge tree). No D1/D2/Outcome/imports/file-scope change; no substrate extension; no novel operator decision (ratified-D3 application). Every genuine finding across all codex reviews is now actually resolved — a fresh codex re-review on d4f57e59c clears legitimately. Not self-merging (operator merges).

— sent from snappy-badger-570

@briansrls

Copy link
Copy Markdown
Contributor Author

APPROVE noted (no rubric violation). The optional exploratory observation is verified ALREADY-CORRECT, not a regression — no action needed.

The header's scaffold Brief: see BRIEF_TEMPLATE.md pointer was not "lost" — it was the standard, sanctioned worker-closeout transformation, matching the merged precedents (std/node.dag, std/diagnostic.dag): on completion the scaffold Status: scaffold … / Brief: see BRIEF_TEMPLATE.md lines become a modeled Status: note, while the load-bearing immutable-contract semantics are preserved verbatim-equivalent — current header retains "The header I/O contract is immutable for downstream workers" and "Splitting this file requires explicit operator ratification (substrate extension = stop signal)". The brief-pointer is a scaffold-state aid; BRIEF_TEMPLATE.md itself defines that the brief POINTS to the file's frozen header contract (not the reverse), so the canonical worker/downstream anchor remains TASKS.md T-4.12 + the (intact) immutable I/O-contract header. node.dag/diagnostic.dag closed out exactly this way — so this is the in-precedent form, not an unsanctioned immutable-header change or a downstream-anchor loss. Not an invariant breach (as you note); verified, not dismissed.

Verified at HEAD 66e69d916 (auto-main-merge-rolled from d4f57e59c; git rev-parse==gh pr view==66e69d916): all genuine codex findings remain resolved (CallBr/CatchSwitch result, the D3-checked block_well_formed), v2-compiler … --target dag → 64 modules, 0 diagnostics. Content-complete + manager-verified. The only open item is the operator's codex re-trigger on the current auto-rolled HEAD → legitimate APPROVE → operator merge. Not self-merging.

— sent from snappy-badger-570

@briansrls
briansrls merged commit fdaf270 into main May 16, 2026
7 checks passed

@briansrls briansrls left a comment

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Review metadata

  • Provider / model: codex / unknown
  • Commit: d4f57e59 · Trigger: schedule
  • Thinking: 293s wall

BLOCKING (2)

Root Cause

  • src/v4/extdeps/languages/llvm_ir.dag identified-struct declarations were modeled as always body-bearing -> make the named-struct body a closed sum such as OpaqueStruct or DefinedStruct.
  • src/v4/extdeps/languages/llvm_ir.dag optional module target configuration was modeled as required identity fields -> introduce typed present/absent carriers for data layout and target triple.

⚠️ Two spec-faithfulness gaps remain in the LLVM IR substrate model.

// name-reference recursion — NOT a self-referential type definition).
type NamedStructDef {
name: Symbol
definition: LlvmType

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

BLOCKING: NamedStructDef.definition is mandatory, but LLVM 18 permits identified structure declarations with no body (%X = type opaque), so valid opaque structs are unrepresentable (P1/P2 extdeps fidelity).

// out-of-scope spec inflation (M3 — model the IR, not every target
// triple); declaring it opaque is the honest boundary, not a fabrication.
type LlvmModule {
data_layout: Symbol

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

BLOCKING: LlvmModule requires data_layout and target_triple even though LLVM 18 says modules may specify each, so valid modules that omit one are unrepresentable (P1/P2 extdeps fidelity).

briansrls added a commit that referenced this pull request May 16, 2026
…ehaviors (IN-B probe PASS) (#3176)

* v4 T-4.9: model extdeps/languages/verilog.dag — HW concurrency as 5 behaviors (IN-B probe PASS)

IN-B probe RESULT: PASS — Verilog hardware concurrency models cleanly
under the existing five L1 behaviors with NO 6th `Concurrent` behavior
and NO core/pipeline change. The probe surfaces the structurally-
correct intra-vs-cross-program partition: intra-program HW concurrency
(parallel always-blocks / continuous assigns within one module) is the
Conj-of-parallel-siblings + Bind-chain-within-always shape, with per-
language effect-typing intrinsic to the wire/reg/vector signal type;
cross-program coordination (Endpoint/DeploymentUnit/messaging) is a
distinct concern owned by extdeps/coordination.dag (T-4.8).

Declares closed-Disj coproducts (each with full 5-pattern Practice-4
ledger — Fact-placement / Variant-is-data / Algebraic-form / Dimensional
/ Parameterized-family-Practice-7 per modeling-discipline.md §4):
PortDirection, NetType, VariableType, EdgeTrigger,
ProceduralAssignKind, PackingShape, ModuleItem. Conj records (no
ledger): VectorRange (🟡 scaffold), NetDeclaration, VariableDeclaration,
PortDeclaration, ParameterDeclaration, SensitivityItem,
ContinuousAssign, AlwaysBlock, InitialBlock, PortConnection,
ModuleInstance, VerilogModule, VerilogCost (🟡 scaffold).

DEFERRED with named-owner+trigger (do not author, do not improvise):
- emit/parse ops ride D1 Outcome<T> (Produced{value:T}|Rejected{...})
  when ratified in std/diagnostic.dag (v4 value-or-Diagnostic STOP
  surfaced by T-4.6 keen-wren-419).
- Bit-vector inhabitance (Semiring<UInt<N>> / OrderedRing<Int<N>>) rides
  pending D2 instance-value form (PR #3171's worker pushback precedent).
- Expression sub-grammar (RHS of assign, procedural-statement bodies,
  control-flow conditions) ride the T-4 LanguageModel bundle; verbatim
  String lexemes carry the textual surface in the interim (spice.dag
  SpiceValue.lexeme precedent).

Scaffold-header Consumes line preserved verbatim with surfaced staleness
(primitive.dag deleted PR #3152; coordination.dag is an unfilled scaffold
modeling cross-program coordination — a different concern from intra-
program HW concurrency). The systemic per-file Consumes reconciliation
is pending operator ratification (T-4 mgr synthesis msg_1fddb75c).

Verification: `v2-compiler compile --source-root src/v4 --target dag`
= 63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: address 3 codex BLOCKING findings on PR #3176 — spec fidelity + structural P2

Fixes from the codex review b12e8bd9 (sha-pinned BLOCKING):

1. NetType: add `TriAnd` + `TriOr` to complete the IEEE 1364-2005 §3.7.1
   net-type table (was 10 variants; spec admits 12 — `triand` and `trior`
   are the designer-intent partners of `wand`/`wor` paired with `tri`,
   syntactically distinct and parse∘emit-preserving per K-1). Ledger
   updated to "twelve-way" with the new paired-partner rationale on
   Practice-7.

2. VariableDeclaration: refactor to Disj-with-named-payloads (`RegVariable
   { name, packing } | IntegerVariable { name } | RealVariable { name } |
   TimeVariable { name } | RealTimeVariable { name }`). Only `RegVariable`
   admits a packing payload; the other four are scalar-only per IEEE
   1364-2005 §5.7 (`[N:M] integer i;` is a syntax error). The prior
   `{ var_type: VariableType, packing: PackingShape }` Conj-record-with-
   independent-coordinates form ratified the illegal state "Integer with
   Packed range" — INVARIANTS P2 illegal-states-unrepresentable anti-
   pattern. The dissolved Disj-with-heterogeneous-payloads shape mirrors
   rust.dag's RustScalar and go.dag's GoScalar precedent. Full 5-pattern
   ledger now lives on `VariableDeclaration`; the `VariableType` enum
   becomes redundant (its discriminator role is subsumed by the variant
   names) and is removed.

3. PortDeclaration: drop `packing: PackingShape` field — single-authority
   via the matching `NetDeclaration` / `VariableDeclaration` in the
   module body (per IEEE 1364-2005 §12.3.3 the inline `input wire [7:0]
   data` form produces TWO items: the port + the matching net
   declaration). The prior duplicate-authority on `packing` was the
   INVARIANTS P2 cost-of-change ≥ 2 anti-pattern the codex review
   surfaced.

Verification: `v2-compiler compile --source-root src/v4 --target dag` =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: add Signedness — preserve IEEE 1364-2005 §5.6 signed/unsigned boundary fact (codex BLOCKING on PR #3176)

codex BLOCKING inline review on PR #3176 verilog.dag:597: NetDeclaration
collapses signed and unsigned packed nets — IEEE 1364-2005 §5.6 admits
`wire signed [N:0]` / `reg signed [N:0]` as a structural fact every
arithmetic and emission consumer must preserve (signedness governs
sign-extension on assignment, comparison semantics, signed-vs-unsigned
operator dispatch). INVARIANTS P2 boundary-fact violation.

Fix:
- New closed-Disj Signedness = Signed | Unsigned with full 5-pattern
  Practice-4 ledger.
- NetDeclaration gains signedness: Signedness (every net-type admits
  the `signed` keyword per spec; even for scalar nets the spec preserves
  the syntactic distinction — parse∘emit identity).
- VariableDeclaration.RegVariable gains signedness: Signedness (per
  spec §5.6 `reg` admits `signed`). The spec-fixed-signedness kinds
  (IntegerVariable always-signed per spec; TimeVariable always-unsigned;
  RealVariable / RealTimeVariable are IEEE-754 floating-point with
  sign internal to the representation) carry NO signedness payload —
  illegal states like "RealVariable signedness=Signed" or "TimeVariable
  signedness=Signed" are unrepresentable by construction (same shape
  as the kind × packing partition).
- VariableDeclaration ledger updated to dissolve the additional kind
  × signedness illegal-state argument (Practice-2 covers BOTH
  packing AND signedness Cartesian products simultaneously).

Verification: v2-compiler compile --source-root src/v4 --target dag =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: add AlwaysBlockSensitivity Disj — represent @* implicit event control (codex BLOCKING on PR #3176)

codex BLOCKING inline review on PR #3176 verilog.dag:749: the prior
`sensitivity: List<SensitivityItem>` on AlwaysBlock could not
represent IEEE 1364-2005 §9.7.2 implicit `@*` / `@(*)` event control
— that form has no explicit signal list (the implicit set is computed
from the body at synthesis/simulation time). Modeling it as an
empty SensitivityItem list collapsed it with "no event control"
(bare `always`). INVARIANTS P1 spec-fidelity violation.

Fix: new AlwaysBlockSensitivity Disj with three variants (the
IEEE 1364-2005 §9.7.2 partition):
- NoEventControl: bare `always begin ... end` (no `@`)
- ImplicitAtStar: `always @*` / `always @(*)` — nullary marker
  (implicit set computed from body, not stored)
- ExplicitEventList { items: List<SensitivityItem> }: explicit list

Full 5-pattern Practice-4 ledger. Each variant carries exactly the
structural data its form admits — heterogeneous payloads make
collapsing to a uniform record reintroduce the prior anti-pattern.

AlwaysBlock.sensitivity now AlwaysBlockSensitivity (replaces
List<SensitivityItem>).

Verification: v2-compiler compile --source-root src/v4 --target dag =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: ModuleItem closed-set-coverage clarification — match spice #3168 deliberate-non-exhaustive framing (codex BLOCKING on PR #3176)

codex BLOCKING inline review on PR #3176 verilog.dag:922: ModuleItem
was marked 🟢 GREEN terminal closed while the file's own comment
admitted scope-negative IEEE 1364-2005 §12.2 items (defparam, generate,
specify, task, function). Internal-consistency concern: the ledger
claimed terminal-spec-fidelity for a scoped subset.

Fix: clarify the framing to match the spice.dag #3168 Component
precedent — the 5-pattern Practice-4 ledger is about COPRODUCT
DISSOLUTION SHAPE (do these variants need to collapse?), NOT
membership completeness. Adding the named scope-negative variants is
MECHANICAL (one variant per kind with body_lexeme payload for the
sub-language portion) and the 5-pattern ledger STAYS UNCHANGED — the
dissolution argument holds across the full spec set, not just the
IN-B-probe-core subset enumerated here. Each pattern's reasoning
extended to explicitly cover what adding the named variants would
preserve.

This is the spice precedent's "deliberate non-exhaustive scoping the
probe permits" framing applied to ModuleItem (spice's Component does
the same: controlled-source E/F/G/H, JFET, transmission line, switches
NOT enumerated in initial cut). No variants added; the framing is
sharpened to be internally consistent — terminal SHAPE, deliberately
non-exhaustive MEMBERSHIP.

Verification: v2-compiler compile --source-root src/v4 --target dag =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: drop stray NetDeclaration banner orphaned by Signedness insertion (cursor APPROVE_WITH_COMMENTS on PR #3176)

cursor/composer-2 APPROVE_WITH_COMMENTS finding (cosmetic): when commit
cb65ea8ca inserted the Signedness block BEFORE the existing NetDeclaration
block, the prior `// NetDeclaration — …` banner remained orphaned at the
Signedness block's position. Real NetDeclaration banner + commentary
follows correctly at line ~660. Removing the orphan banner so the
Signedness section has its own clean header.

Verification: v2-compiler compile --source-root src/v4 --target dag =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: model positional port connections — PortConnections Disj (codex BLOCKING on PR #3176)

codex BLOCKING inline review on PR #3176 verilog.dag:999: PortConnection
modeled only named (`.port(signal)`) connections while my own comment
admitted IEEE 1364-2005 §12.1.2 also accepts positional connections
(`Adder a1 (sig1, sig2, sig3)`). INVARIANTS P1 modeling-faithfulness
violation — spec admits both forms; declaring positional as scope-
negative excluded valid Verilog syntax.

Fix — Disj-with-named-payloads at the port-binding-list level (where
the spec's per-instance uniformity constraint lives):
- Renamed PortConnection → NamedPortConnection (the per-entry named
  connection record stays the same Conj shape: port + signal).
- New PortConnections coproduct = PositionalConnections { signals:
  List<Symbol> } | NamedConnections { connections: List<NamedPortConnection> }.
  Full 5-pattern Practice-4 ledger.
- ModuleInstance.connections is now PortConnections (replaces
  List<PortConnection>).

Result: the spec's per-instance uniform-form choice (mixed positional
+named within ONE instance is a syntax error per spec) is structurally
enforced — "mixed positional+named" is unrepresentable by construction.
Positional connections are now first-class, no longer scope-negative.

Verification: v2-compiler compile --source-root src/v4 --target dag =
63 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: address openai-pro REQUEST_CHANGES — port-connection expressions, ANSI/non-ANSI port styles, VectorRange negative-index spec fidelity (PR #3176)

openai-pro/gpt-5.5-pro REQUEST_CHANGES on PR #3176 at sha c2f06ff1
surfaced three substantive IEEE 1364-2005 spec-fidelity gaps. All
three are in-pattern declaration-class refinements:

1. PORT-CONNECTION ACTUAL was modeled as `signal: Symbol`, narrowing
   to identifier references. Per spec §12.1.2 the actual can be any
   expression (`.en(1'b1)`, `.data(bus[3:0])`, `.sum(a + b)`) or
   blank (`.unused()`). INVARIANTS P1 modeling-faithfulness violation.

   Fix: new closed-Disj PortConnectionActual = ExpressionConnection {
   expression_lexeme: String } | BlankConnection. NamedPortConnection
   now carries `actual: PortConnectionActual` (replaces `signal:
   Symbol`). PositionalConnections carries `actuals: List<
   PortConnectionActual>` (replaces `signals: List<Symbol>`). Full
   5-pattern Practice-4 ledger. Expression sub-grammar deferred to
   T-4 LanguageModel via verbatim lexeme — same body_lexeme precedent
   as AlwaysBlock / ContinuousAssign / spice.dag SpiceValue.

2. PORT DECLARATION SINGLE-AUTHORITY was over-applied to ANSI-style
   ports. Per spec §12.3.3 ANSI-style ports carry their type INLINE
   (`module M (input wire [7:0] data, output reg b, …);`) and body
   redeclaration is a syntax error. The prior "type-fact lives
   EXCLUSIVELY in matching body declaration" rule was correct for
   non-ANSI (Verilog-1995) style but wrong for ANSI (Verilog-2001 /
   1364-2005 §12.3.3) style. INVARIANTS P1/P2 violation — the model
   forced all ports to depend on a synthetic matching body item.

   Fix: new closed-Disj PortDeclarationStyle = NonAnsiStyle |
   AnsiStyle { net_kind, packing, signedness }. PortDeclaration now
   carries `style: PortDeclarationStyle`. AnsiStyle carries
   PortAnsiTypeKind = AnsiNetType { net_type: NetType } |
   AnsiVariableType { var_kind: AnsiVariableKind } (the ANSI-port
   type-kind partition, mirroring NetType / VariableDeclaration body
   forms). AnsiVariableKind = AnsiReg | AnsiInteger | AnsiReal |
   AnsiTime | AnsiRealTime (matches the body-side variable-kind
   set). Full 5-pattern Practice-4 ledger on each new Disj. Both
   styles preserve P2 single-authority — just at different loci per
   spec.

3. VECTORRANGE scaffold (b)-bound incorrectly excluded negative
   indices. Per spec §3.10, msb and lsb constant expressions can be
   positive, negative, OR zero (`reg [-1:4] b;` is a spec example).
   The prior bound classified legal Verilog as a producer bug.

   Fix: corrected the scaffold (b)/(c) bounds to admit the spec's
   full signed-Int range for msb/lsb (including negative); the
   bounded-cardinality refinement is the eventual terminal shape,
   but it must admit the spec range, not exclude it.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics (64 reflects std/verification.dag #3183
landing on main).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: module-level port-list style Disj + ModuleInstance parameter-overrides (codex BLOCKING on PR #3176)

codex BLOCKING at sha 96f57080 surfaced two substantive spec-fidelity
gaps. Both in-pattern declaration-class refinements:

1. PORT-LIST STYLE was modeled as a PER-PORT `style: PortDeclaration
   Style` field, which admitted the IEEE 1364-2005 §12.3.4 spec-
   forbidden mixed-style state within one module. The spec admits two
   port-list styles (non-ANSI / ANSI) MUTUALLY EXCLUSIVE PER MODULE —
   the style choice belongs on the module's port-list as a whole.

   Fix:
   - Removed PortDeclarationStyle Disj (dissolved into the new
     module-level partition).
   - PortDeclaration now carries only direction + name (the non-ANSI
     form — type-fact in matching body declaration).
   - New AnsiPortDeclaration Conj record carries direction + name +
     net_kind + packing + signedness inline (the ANSI form per spec
     §12.3.3).
   - New closed-Disj ModulePortsList = NonAnsiPorts { ports:
     List<PortDeclaration> } | AnsiPorts { ports:
     List<AnsiPortDeclaration> } with full 5-pattern Practice-4
     ledger.
   - VerilogModule.ports now ModulePortsList (replaces
     List<PortDeclaration>). Mixed-style within one module is
     unrepresentable by construction.

2. MODULE INSTANCE OMITTED parameter-override carrier (`Adder
   #(.WIDTH(8)) a1 (...)` per spec §12.1.3). The prior ModuleInstance
   had module_name + instance_name + connections only; the §12.1
   parameterized-instantiation surface was unrepresentable.

   Fix:
   - New ParameterOverrides Disj = NoParameterOverrides |
     OrderedParameterOverrides { actuals: List<String> } |
     NamedParameterOverrides { overrides: List<NamedParameterOverride> }
     with full 5-pattern Practice-4 ledger. Expression-actuals carried
     as verbatim lexemes per the body_lexeme precedent. Mixed
     ordered+named within one #(...) clause is unrepresentable per
     spec.
   - ModuleInstance now carries parameter_overrides: ParameterOverrides
     before connections.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: PortAnsiTypeKind per-variant packing/signedness payloads — illegal ANSI states unrepresentable (codex BLOCKING on PR #3176)

codex BLOCKING inline review on PR #3176: my prior AnsiPortDeclaration
uniformly applied `packing` + `signedness` to every variant of
PortAnsiTypeKind (including AnsiVariableKind = AnsiInteger / AnsiReal
/ AnsiTime / AnsiRealTime), but IEEE 1364-2005 §3.7.2 / §5.6 forbid
packing AND signedness modifiers on integer/real/time/realtime
variable kinds (integer is spec-fixed 32-bit signed; real / realtime
are floating-point; time is spec-fixed 64-bit unsigned). The
uniform-payload encoding admitted spec-forbidden states like `output
integer signed [N:0]`. INVARIANTS P2 illegal-states-unrepresentable
violation — same shape my body-side VariableDeclaration Disj
already dissolves.

Fix:
- Restructured PortAnsiTypeKind from a two-variant Disj
  (AnsiNetType / AnsiVariableType { var_kind: AnsiVariableKind }) to
  a SIX-variant Disj-with-heterogeneous-payloads:
    AnsiNetType { net_type, packing, signedness }
    AnsiRegType { packing, signedness }
    AnsiIntegerType                           // no packing, no sign
    AnsiRealType                              // no packing, no sign
    AnsiTimeType                              // no packing, no sign
    AnsiRealTimeType                          // no packing, no sign
- Dissolved AnsiVariableKind (the nullary 5-way enum subsumed by
  per-variant payloads on PortAnsiTypeKind).
- AnsiPortDeclaration dropped its uniform packing + signedness fields
  (now per-variant on type_kind). Mirror of body-side
  VariableDeclaration's kind × packing × signedness dissolution.
- Full 5-pattern Practice-4 ledger on the new PortAnsiTypeKind.

Result: illegal states like `output integer signed`, `output real
[7:0]`, `output time signed`, `output realtime [N:0]` are
unrepresentable by construction. Mirrors body-side VariableDeclaration
P2 dissolution.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: ModuleItem exhaustive — add defparam/generate/specify/task/function variants (codex REQUEST_CHANGES on PR #3176)

codex/codex-default REQUEST_CHANGES on PR #3176: ModuleItem's prior
"deliberately non-exhaustive" framing (spice.dag #3168 precedent
reference) was insufficient for spec-fidelity — the spec partition
includes defparam (§4.10.2.1), generate (§12.4), specify (§14), task
(§10.2), and function (§10.3) declarations as legal module items, so
a closed-Disj claiming IEEE 1364-2005 §12.2 fidelity must include
them.

Fix:
- Added 5 supporting Conj records:
  - DefparamDeclaration { target_path: String, value_lexeme: String }
  - GenerateRegion { body_lexeme: String }
  - SpecifyBlock { body_lexeme: String }
  - TaskDeclaration { name: Symbol, body_lexeme: String }
  - FunctionDeclaration { name: Symbol, body_lexeme: String }
  Each defers its sub-language body to the bundled T-4 LanguageModel
  productions via the established body_lexeme precedent (same shape
  as AlwaysBlock.body_lexeme / ContinuousAssign.rhs_lexeme).
- Added 5 ModuleItem variants:
  - DefparamDeclarationItem
  - GenerateRegionItem
  - SpecifyBlockItem
  - TaskDeclarationItem
  - FunctionDeclarationItem
- Updated ModuleItem ledger from "deliberately non-exhaustive" to
  twelve-way exhaustive over the §12.2 partition; each pattern's
  argument extended to cover the new variants (Variant-is-data
  payload-list extended; Parameterized-family argument notes the
  new variants preserve heterogeneity).
- Removed the spice.dag non-exhaustive-precedent reference from
  ModuleItem (the framing is now exhaustive; the spice precedent
  remains the right framing for spice's own Component partition).

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: 3 codex BLOCKINGs — ANSI direction×type-kind partition, lexeme consistency, ModuleItem exhaustive (PR #3176)

codex/codex-default REQUEST_CHANGES at sha 9cbec173 surfaced three
spec-fidelity gaps. All in-pattern:

1. ANSI DIRECTION × TYPE-KIND was a product axis (direction + type_kind
   independent), admitting spec-forbidden combinations like
   `input reg [N:0]` and `inout integer` (per IEEE 1364-2005 §12.3.3
   input/inout ports MUST be net-typed; only output ports admit
   variable kinds reg/integer/real/time/realtime).

   Fix: restructured AnsiPortDeclaration into a per-direction Disj:
     AnsiInputPort { name, net: AnsiNetPortType }     // net-only
     AnsiOutputPort { name, type_kind: PortAnsiTypeKind }  // full set
     AnsiInoutPort { name, net: AnsiNetPortType }     // net-only
   New AnsiNetPortType Disj carries the net-only payload (single
   AnsiInputInoutNet variant currently). Full 5-pattern Practice-4
   ledger on each new Disj. Mirror of body-side VariableDeclaration's
   per-kind admissibility dissolution.

2. LEXEME CONSISTENCY — SensitivityItem.signal was Symbol (narrowed
   to identifier references; spec §9.7.2 admits any expression);
   ContinuousAssign.lhs was Symbol (narrowed to identifier; spec §6.1
   admits net_lvalue forms — bit-select, part-select, concat).

   Fix:
   - SensitivityItem.signal: Symbol → event_expression_lexeme: String
   - ContinuousAssign.lhs: Symbol → lhs_lexeme: String
   Both sub-grammars deferred to T-4 LanguageModel via established
   body_lexeme precedent.

3. MODULEITEM STILL INCOMPLETE — the prior 12-variant cut missed
   event_declaration (§9.7.3), genvar_declaration (§12.4.2),
   local_parameter_declaration (§3.10), gate_instantiation (§7),
   udp_instantiation (§8), and specparam_declaration (§14.3.1) per
   the full §12.2 + §14.3.1 grammar.

   Fix: added 6 new Conj records (EventDeclaration, GenvarDeclaration,
   LocalParameterDeclaration, GateInstantiation, UdpInstantiation,
   SpecparamDeclaration) each with body_lexeme deferral for their
   sub-language portion. ModuleItem expanded from 12 to 18 variants;
   ledger updated to note the §12.2 + §14.3.1 exhaustive coverage.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: separate non-ANSI header port-list from body port_declaration (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176 at sha 949f421fb (1755): non-ANSI module
header was carrying PortDeclaration { direction, name } as a header
element, but per IEEE 1364-2005 §12.3.2 non-ANSI headers carry only
port-expressions (port-names or bit-selects); direction is a BODY
port_declaration item per §12.3.4 + §12.2 module_item grammar. The
prior shape collapsed the spec's header-vs-body partition AND made
ModuleItem's §12.2 closed-set coverage incomplete (body
port_declarations are §12.2 items the prior 18-way cut omitted).

Fix:
- New NonAnsiPort Conj record carrying `port_expression_lexeme:
  String` — covers port-name + bit-select + renamed-port forms via
  the established body_lexeme precedent.
- ModulePortsList.NonAnsiPorts.ports now List<NonAnsiPort> (was
  List<PortDeclaration>). Non-ANSI headers carry expressions only;
  direction lives in body items.
- PortDeclaration { direction, name } stays as a body item carrier
  (unchanged shape; relocated semantically).
- ModuleItem gains 2 new variants:
  - PortDeclarationItem { port_decl: PortDeclaration } — body
    direction-only port_declaration (`input a;`).
  - BodyPortDeclarationItem { body_port: AnsiPortDeclaration } —
    body port_declaration with inline type (`input wire [7:0] a;`),
    reusing AnsiPortDeclaration's per-direction Disj structure
    since the body combined form is shape-equivalent to ANSI per
    §12.3.4.
- ModuleItem ledger updated 18→20 variants; closed-set-coverage
  note explains the header/body separation + the
  AnsiPortDeclaration carrier reuse for body's combined form.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: ModuleParameterPortList — model module-header #(parameter W = 8) clause per §12.1 (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: VerilogModule had no carrier for the
IEEE 1364-2005 §12.1 module_parameter_port_list — the optional
`module M #(parameter W = 8, parameter D = 16) (...)` clause was
unrepresentable, collapsing header parameters with body
ParameterDeclarationItem. Header parameters are spec-distinct from
body parameters: header parameters are externally overridable via
instantiation `#(...)` syntax (ParameterOverrides on ModuleInstance);
body parameters are not.

Fix:
- New closed Disj ModuleParameterPortList = NoModuleParameterPortList
  | ModuleParameters { parameters: List<ParameterDeclaration> }
  with full 5-pattern Practice-4 ledger. Explicit "no clause" vs
  "with parameters" distinction (Disj-with-named-payloads).
- VerilogModule.parameter_port_list: ModuleParameterPortList field
  added between name and ports. The §12.1 header structure is now
  faithfully ordered: name → optional #(...) parameters → ports →
  body items.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: VerilogModule per-style Disj — body items × port-style admissibility (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: items: List<ModuleItem> was unrestricted
by port style — an ANSI-port module could carry body
PortDeclarationItem / BodyPortDeclarationItem, but per IEEE 1364-2005
§12.3.3 ANSI ports are "completely declared" and body redeclarations
are a syntax error. INVARIANTS P2 illegal-states-unrepresentable
violation.

Fix:
- Split ModuleItem into AnsiModuleItem (18 variants — all of the
  prior set EXCEPT PortDeclarationItem and BodyPortDeclarationItem)
  and NonAnsiModuleItem (3 variants — NonAnsiAnsiCompatItem wrapping
  an AnsiModuleItem + NonAnsiPortDeclarationItem +
  NonAnsiBodyPortDeclarationItem).
- Dissolved the standalone ModulePortsList Disj; lifted port-style
  choice to VerilogModule itself.
- VerilogModule is now a Disj:
  - NonAnsiVerilogModule { name, parameter_port_list, header_ports:
    List<NonAnsiPort>, items: List<NonAnsiModuleItem> }
  - AnsiVerilogModule { name, parameter_port_list, header_ports:
    List<AnsiPortDeclaration>, items: List<AnsiModuleItem> }

Result: "ANSI port-list module with body port_declaration items" is
unrepresentable by construction. The §12.3.4 module-style partition
is structural at the module-as-a-whole level; both header port-list
type AND body items admissibility are per-variant on VerilogModule's
Disj.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: PrimitiveGateKind closed Disj — replace free gate_keyword String (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: GateInstantiation.gate_keyword was a free
String even though IEEE 1364-2005 §7 admits a closed 26-keyword
primitive-gate set. MODELING M4 closed-sets-are-enums-not-strings +
INVARIANTS P2 illegal-states-unrepresentable violation.

Fix: new closed PrimitiveGateKind Disj over the 26 spec gate types
across six families per §7:
- N-input: GateAnd / GateNand / GateOr / GateNor / GateXor / GateXnor
- N-output: GateBuf / GateNot
- Three-state: GateBufif0 / GateBufif1 / GateNotif0 / GateNotif1
- MOS: GateNmos / GatePmos / GateCmos / GateRnmos / GateRpmos / GateRcmos
- Bidirectional: GateTran / GateRtran / GateTranif0 / GateTranif1 /
  GateRtranif0 / GateRtranif1
- Pull: GatePulldown / GatePullup
Full 5-pattern Practice-4 ledger.

GateInstantiation.gate_keyword: String → gate_kind: PrimitiveGateKind.
Body lexeme deferral unchanged (terminal-arity/drive-strength/delay
admissibility lives in T-4 LanguageModel).

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: declarator carriers + output-port subset + module-style ledger + parameter-surface clarification (codex 4 BLOCKINGs on PR #3176)

codex BLOCKING summary at sha 89ed5916 surfaced 4 spec-fidelity gaps.
All in-pattern declaration-class refactors:

1. DECLARATION-BOUNDARY FACTS COLLAPSED. NetDeclaration / Variable
   Declaration carried name-only, missing strength/delay/dimensions/
   initializer/multi-declarator facts per IEEE 1364-2005 §A.2.1.3 /
   §A.2.4 / §3.10.

   Fix:
   - NetDeclaration now carries net_type + packing + signedness +
     drive_strength_lexeme + delay_lexeme + declarators:
     List<NetDeclarator>. NetDeclarator { name, initializer_lexeme }
     covers list_of_net_decl_assignments per spec.
   - VariableDeclaration variants restructured: each carries
     declarators: List<VariableDeclarator> instead of single name.
     VariableDeclarator { name, unpacked_dimensions_lexeme,
     initializer_lexeme } covers list_of_variable_decl_assignments +
     unpacked-array dimensions per spec §7.4.

2. MODULE PARAMETER AUTHORITY split by header location. The §12.1
   overrideable-parameter surface is the UNION of header parameter_
   port_list + body ParameterDeclarationItem (excluding Local
   ParameterDeclarationItem per §3.10).

   Fix: clarified VerilogModule commentary to document the unified
   parameter-overrideable surface — instantiation #(...) overrides
   bind to the projection union of header+body parameter declarations
   in source order, excluding localparam. Structural carrier remains
   the per-variant items list; the unified surface is the projection
   the binding consumer walks.

3. OUTPUT PORT TAXONOMY admitted spec-forbidden real/realtime
   outputs (per §12.3.3 "An output port can be of any net or
   variable type EXCEPT a real type").

   Fix: new OutputPortAnsiTypeKind closed Disj (4 variants:
   OutputAnsiNetType / OutputAnsiRegType / OutputAnsiIntegerType /
   OutputAnsiTimeType) — real/realtime outputs unrepresentable by
   construction. AnsiOutputPort.type_kind: PortAnsiTypeKind →
   OutputPortAnsiTypeKind.

4. VERILOGMODULE DISJ MISSED 5-pattern Practice-4 ledger (a new
   substrate Disj introduced in commit ec34a6b5a without the
   modeling-discipline.md §4 required ledger).

   Fix: added full 5-pattern ledger to VerilogModule — each pattern
   covers the per-style structural shape, illegal-states-
   unrepresentable argument (ANSI-with-body-port-decl dissolution),
   the §12.3.4 module-style partition framing.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: ParameterDeclaration / LocalParameterDeclaration / SpecparamDeclaration multi-assignment + type-kind facts (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: ParameterDeclaration stored only
{ name, default_lexeme } — missing type/range/signedness facts that
per IEEE 1364-2005 §A.2.1.1 govern §12.1.3 override conversion.
INVARIANTS P2 boundary-fact preservation.

Fix:
- New ParameterTypeKind closed Disj = UntypedParameter { packing,
  signedness } | IntegerParameter | RealParameter | TimeParameter |
  RealTimeParameter — covers the spec §A.2.1.1 parameter-type
  partition; UntypedParameter is the only variant carrying
  range+signedness per spec (explicit-typed forms forbid those
  modifiers). Full 5-pattern Practice-4 ledger.
- New ParameterAssignment Conj record { name, default_lexeme } —
  covers list_of_param_assignments per spec §A.2.4.
- ParameterDeclaration restructured: { type_kind: ParameterTypeKind,
  assignments: List<ParameterAssignment> }. Multi-assignment per
  spec (`parameter W = 8, D = 16;` is one declaration with 2
  assignments).
- LocalParameterDeclaration restructured similarly (same shape
  per spec).
- SpecparamDeclaration restructured: { packing: PackingShape,
  assignments: List<ParameterAssignment> } — specparams admit
  optional range but no type-kind per §14.3.1 / §A.2.1.1.

The §12.1.3 override conversion machinery now has the spec-mandated
type-kind facts available; illegal forms like `parameter integer X =
8, signed [3:0] Y = 4'sb1100` (mixing typed + range modifiers) are
unrepresentable by construction.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: 3 openai-pro REQUEST_CHANGES — generate constructs, parameter-override conditional, optional-clause sentinels (PR #3176)

openai-pro REQUEST_CHANGES at sha 051aa561 surfaced 3 substantive
findings. All in-pattern declaration-class spec-fidelity:

1. GENERATE CONSTRUCTS — per IEEE 1364-2005 Annex A.1.4
   loop_generate_construct and conditional_generate_construct are
   admitted DIRECTLY at module_or_generate_item level, not nested
   inside `generate ... endgenerate`. The prior GenerateRegionItem
   covered only the `generate ... endgenerate` form, omitting bare
   `for (genvar ...) ...` and `if/case (cond) ...` generate-block
   forms.

   Fix: new LoopGenerateConstruct + ConditionalGenerateConstruct
   Conj records (each with body_lexeme deferral). Added
   LoopGenerateConstructItem + ConditionalGenerateConstructItem
   variants to AnsiModuleItem (which propagate to NonAnsiModuleItem
   via NonAnsiAnsiCompatItem wrapping).

2. PARAMETER-OVERRIDE CONDITIONAL RULE — VerilogModule commentary
   was internally inconsistent: one block said overrides bind to
   header parameters only; another said header+body. Per spec §12.1
   the rule is CONDITIONAL: when header `#(...)` is present, body
   `parameter` declarations are LOCAL (not overrideable); when no
   header `#(...)`, body `parameter` declarations ARE the
   overrideable surface. (`localparam` is never overrideable per
   §3.10.)

   Fix: rewrote both VerilogModule and ModuleParameterPortList
   commentary blocks with the §12.1 conditional rule explicitly
   stated. Each NoModuleParameterPortList / ModuleParameters
   variant docs which surface IS overrideable for that variant.

3. OPTIONAL-CLAUSE EMPTY-STRING SENTINELS — 5 fields used `""
   = absent` String sentinel for optional clauses (drive_strength_
   lexeme, delay_lexeme, initializer_lexeme on NetDeclaration /
   NetDeclarator; unpacked_dimensions_lexeme, initializer_lexeme on
   VariableDeclarator). The file's own PortConnectionActual rejected
   this exact pattern in favor of a closed BlankConnection variant.
   Inconsistent + INVARIANTS P3 / C-9 / P5 untracked-sentinel debt.

   Fix: 5 new closed Disjs (DriveStrengthClause, DelayClause,
   NetInitializerClause, UnpackedDimensionsClause,
   VariableInitializerClause), each a 2-way present-or-absent
   partition with the Lexeme variant carrying the verbatim lexeme.
   Full 5-pattern Practice-4 ledgers (the first one is verbose; the
   following ones use the same argument shape with abbreviated form
   per the established pattern). NetDeclaration / NetDeclarator /
   VariableDeclarator field types updated to the new Disjs.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: revert NonEmptyList<T> form per T-4 mgr disposition — defer to std/collection.dag Wave-A2 refinement (RQ-3)

T-4 mgr (vivid-carp-207) msg_30a7ec7c disposition: HOLD on
NonEmptyList<T> form. Three anchors:

1. CANONICAL FORM resolved by docs/coercion-design.md RQ-3:
   "refinements of base containers, NOT separate inhabitant
   families. NonEmptyList<T> = List<T> where non_empty. Separate
   inhabitants would grow the authority surface." The hand-rolled
   `type NonEmptyList<T> { head: T, tail: List<T> }` IS a separate
   inhabitant family — breaks the ratified Vec<T> coercion.
2. The canonical `List<T> where non_empty` refinement is NOT yet
   expressible in merged v4 (no where-refinement substrate landed).
   std/collection.dag merged-on-main DEFERS its finite-cardinality/
   refinement layer to "Wave-A2 — TRACKED SCAFFOLD (🟡)".
3. verilog.dag's frozen scaffold header neither Owns nor Consumes
   std/collection.dag. Minting a parallel non-empty carrier in a
   leaf language probe would be a 5-language parallel-declaration
   precedent — the v3 cross-layer spine-drift this T-4 directive
   exists to prevent.

Sanctioned deferral middle-path:
- Removed `type NonEmptyList<T>` declaration.
- Reverted all 6 spec-non-empty sites to `List<T>`:
  - NetDeclaration.declarators
  - VariableDeclaration.{Reg,Integer,Real,Time,RealTime}Variable.declarators
  - ParameterDeclaration.assignments
  - LocalParameterDeclaration.assignments
  - SpecparamDeclaration.assignments
  - ModuleParameters.parameters
- Replaced the prior NonEmptyList declaration block with a shared
  🟡 TRACKED-SCAFFOLD note documenting:
  - The codex empty-list-illegal-state motivation (spec-correct).
  - RQ-3's "refinements over base containers, not separate
    inhabitants" authority (foreclosing the worker-mint).
  - std/collection.dag Wave-A2 deferral (the canonical refinement
    substrate's tracked location).
  - The frozen-header scope argument (no Consume on
    collection.dag).
  - DISSOLUTION TRIGGER: when std/collection.dag Wave-A2 lands the
    non-empty refinement, the six sites adopt
    `List<T> where non_empty` uniformly in one sweep.

The empty-list state is a producer-side invariant pending the
refinement substrate. The codex obligation is real but it is a
DEFERRED refinement obligation, not a verilog-local carrier mint.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: extend non-empty-list deferral to 3 additional sites + add per-site back-pointers (codex REQUEST_CHANGES; manager-relayed)

codex REQUEST_CHANGES at sha f87fdf189 flagged 3 additional spec-non-
empty list fields (the prior NonEmptyList<T> shape had been reverted
per T-4 mgr disposition msg_30a7ec7c — RQ-3 / collection.dag Wave-A2
deferral):
- ExplicitEventList.items (§9.7.2): explicit @(...) form requires ≥1
- OrderedParameterOverrides.actuals (§12.1.3): present #(...) clause
  with zero actuals is redundant with NoParameterOverrides AND
  spec-illegal
- NamedParameterOverrides.overrides (§12.1.3): same shape

Per manager-relayed disposition msg_30a7ec7c + msg_38dd2617: the
codex motivation is spec-correct, but the FORM is the deferred
refinement (`List<T> where non_empty` per RQ-3, owned by
std/collection.dag Wave-A2), NOT a worker-minted carrier in this
file. Same disposition applies to the 3 new sites.

Fix:
- Updated shared 🟡 TRACKED-SCAFFOLD note's enumeration 6→9 sites
  (added sites 7-9 covering ExplicitEventList.items + both
  ParameterOverrides variants).
- Added terse per-site `// 🟡 spec-non-empty (§<x>) — deferred to
  std/collection.dag Wave-A2 refinement; see shared TRACKED-
  SCAFFOLD note above` back-pointers at all 9 sites (the 6 prior
  + 3 new), per manager's preferred form msg_38dd2617 "ONE shared
  note + terse per-site back-pointer".

No type-shape changes; all 9 fields remain List<T> pending the
collection.dag Wave-A2 refinement.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: split shared OrderedParameterOverrides marker into 9th per-site back-pointer (T-4 mgr msg_341befa3 residual)

T-4 mgr verify-caught residual on 1c404c291: 8 of 9 enumerated
non-empty-list sites carried the inline `🟡 spec-non-empty` back-
pointer; OrderedParameterOverrides was covered by a SHARED marker
above the variant pair (Ordered + Named) but did not have its own
identical-form inline marker — broke the single-grep-token
dissolution-sweep property by exactly one site.

Fix: split the prior shared marker into TWO per-variant markers,
each with the byte-identical `🟡 spec-non-empty (§12.1.3) — deferred
to std/collection.dag Wave-A2 \`List<T> where non_empty\` refinement;
see shared TRACKED-SCAFFOLD note above` token. Now all 9 sites carry
the uniform grep-token; `grep -c "🟡 spec-non-empty (§"` returns 9.

Comment-only, additive. The shared TRACKED-SCAFFOLD note's
enumeration unchanged.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: NonAnsiModuleItem — add required 5-pattern Practice-4 ledger (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: NonAnsiModuleItem Disj (introduced in
ec34a6b5a as part of the VerilogModule per-style restructure)
carried no 5-pattern Practice-4 ledger, violating modeling-
discipline.md §4 binding (every new substrate Disj needs the
🟢/🟡/🔴 classification + 5-pattern ledger).

Fix: added full 5-pattern Practice-4 ledger to NonAnsiModuleItem
with 🟢 GREEN classification. Each pattern's argument covers the
3-way non-ANSI item-set partition (NonAnsiAnsiCompatItem
wrapper + the two body port_declaration forms per §12.3.4); the
membership-vs-style admissibility constraint lives at the
VerilogModule-Disj level (already documented in VerilogModule's
own ledger). Comment-only, additive.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: VectoredessClause — separate §A.2.1.3 net-vectoring clause from drive_strength (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: NetDeclaration commentary previously said
the vectored/scalared modifier was "collapsed into the strength
lexeme position" — but per IEEE 1364-2005 §A.2.1.3 grammar
vectored/scalared is a SEPARATE optional clause between
drive_strength and signed, not part of drive_strength. The collapse
overloaded two distinct §A.2.1.3 declaration-boundary facts.
INVARIANTS P1/P2 boundary-fact preservation.

Fix:
- New closed VectoredessClause Disj = NoVectoredness | VectoredNet |
  ScalaredNet with full 5-pattern Practice-4 ledger. The 3-way
  partition makes the spec-forbidden "both vectored and scalared"
  state unrepresentable (a `{ vectored: Bool, scalared: Bool }`
  proxy admits the illegal combination).
- NetDeclaration gains `vectoredness: VectoredessClause` field
  between drive_strength and delay (matching the §A.2.1.3 grammar
  clause-ordering for clarity).
- NetDeclaration commentary corrected: vectored/scalared is now
  noted as a SEPARATE §A.2.1.3 declaration-boundary fact carried
  via the dedicated VectoredessClause; the prior collapse-into-
  drive_strength framing was wrong.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: ModuleInstantiation — multi-instance form with shared module_name + parameter_overrides per §A.4.1.1 (codex BLOCKING on PR #3176)

codex BLOCKING on PR #3176: prior ModuleInstance modeled ONE instance
per carrier (one module_name + one parameter_overrides + one
instance_name + one connections), losing the §12.1 / §A.4.1.1
multi-instance form `Adder #(.W(8)) a1 (.a(x1)), a2 (.a(x2));` —
where one module_instantiation statement carries ONE shared
(module_name, parameter_overrides) and a non-empty list of
(instance_name, connections) entries. The shared statement-boundary
and parameter-override authority were lost. INVARIANTS P1/P2.

Fix:
- Refactored ModuleInstance to per-instance entry: { instance_name,
  connections } — drops module_name + parameter_overrides (those
  are shared at the instantiation level).
- New ModuleInstantiation Conj record { module_name,
  parameter_overrides, instances: List<ModuleInstance> } per spec
  §A.4.1.1 — the shared-clause + per-instance-list shape.
- ModuleItem variant renamed: ModuleInstanceItem →
  ModuleInstantiationItem { instantiation: ModuleInstantiation }.
- Site 11 added to shared 🟡 TRACKED-SCAFFOLD note enumeration
  (ModuleInstantiation.instances per §A.4.1.1) with the inline
  per-site back-pointer marker matching the uniform grep-token form.
  grep -c '🟡 spec-non-empty (§' = 11.

Multi-instance forms now structurally representable; shared
statement-level facts preserved.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: VerilogDesignElement — file-level design-element carrier per spec §A.1.1 (codex top-level BLOCKING on PR #3176)

codex top-level BLOCKING summary at sha 16c992f3: module-body
coverage was closed before the top-level Verilog description
boundary was modeled. UdpDefinition added in 23d8db021 lived as a
sibling type of VerilogModule but had no wrapping Disj — the spec
§A.1.1 source_text design-element partition was implicit.

Fix: new closed VerilogDesignElement Disj = ModuleDesignElement
{ module_decl: VerilogModule } | UdpDesignElement { udp_def:
UdpDefinition } with full 5-pattern Practice-4 ledger. The
spec-admitted third variant `config_declaration` is scope-negative
for T-4.9 per the header PROBE LIMITS (configuration is an
elaboration-time concern outside the IN-B probe); the Disj covers
the two in-scope file-level design elements.

The bundled T-4 LanguageModel grammar productions consume this
Disj when walking the file-level design-element list; the carrier
makes the §A.1.1 partition structural at the top level.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: revert VerilogDesignElement local-mint per T-4 mgr disposition — defer source_text aggregator to canonical T-4 LanguageModel (TASKS.md:504)

T-4 mgr (vivid-carp-207) msg_f2a511b6 disposition: HOLD on
VerilogDesignElement local mint. The 0c797c086 carrier contradicted
my own (and manager-blessed) FILE-LEVEL DESIGN-ELEMENT NOTE from
23d8db021, which named the bundled T-4 LanguageModel grammar-
productions as the owner of the source_text design-element
classifier. Three anchors:

1. TASKS.md:504 (verbatim, dispositive): "A local Byte/Word copy
   or private language-model schema is invalid." The source_text
   design-element classifier IS the canonical LanguageModel
   contract spine (top-level compilation-unit composition), not
   verilog-private grammar. Minting it locally is the v3 cross-
   layer spine-drift the canonical-first directive exists to kill.
2. P2 single-authority + canonical-LanguageModel-first directive:
   the design-element aggregator is owned by the canonical T-4
   LanguageModel grammar-productions work — already the named
   owner in UdpDefinition's FILE-LEVEL DESIGN-ELEMENT NOTE.
3. Codex's gap finding is spec-right (the §A.1.1 partition should
   exist somewhere), but the FORM is the deferred canonical-
   LanguageModel obligation, not a verilog-local mint. Same
   pattern as the NonEmptyList → std/collection.dag Wave-A2
   deferral.

Sanctioned deferral middle-path:
- Removed `type VerilogDesignElement` and its ModuleDesignElement
  / UdpDesignElement variants. The local mint is gone.
- Replaced the declaration block with a deferral-note comment block
  that explicitly cites TASKS.md:504 + P2 + the named-owner
  (bundled T-4 LanguageModel grammar productions) + the dissolution
  trigger.
- Tightened the FILE-LEVEL DESIGN-ELEMENT NOTE in UdpDefinition's
  commentary to explicitly state "verilog.dag does NOT mint the
  design-element Disj locally" per TASKS.md:504, P2, and the
  canonical-LanguageModel-first directive. Added the dissolution-
  trigger clause.

The §A.1.1 design-element gap is a producer-side / canonical-
LanguageModel-owner obligation; the in-scope vocabulary carriers
(VerilogModule + UdpDefinition) remain declared at file scope as
the named owner's input.

Verification: v2-compiler compile --source-root src/v4 --target dag
= 64 modules / 0 diagnostics.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: fix openai-pro REQUEST_CHANGES on PR #3176 sha 6f587e6c

Three findings, all spec-right, addressed in one bundle (manager
disposition from vivid-carp-207 msg_8c2cf95f):

1. BLOCKING — NetDeclaration Conj → 4-way Disj per IEEE 1364-2005
   §A.2.1.3. The prior free-product shape admitted drive_strength on
   the identifier-only form, charge_strength on a non-trireg form,
   mixed init/non-init declarator lists, identifier-only-with-
   initializer, and assignment-form-without-initializer (P2 illegal-
   states-representable). Replaced with the four spec alternatives:
   NonTriregIdentifierForm / NonTriregAssignForm / TriregIdentifierForm
   / TriregAssignForm. The {trireg?} × {form: identifier-only vs
   assignment} partition is STRUCTURAL per variant — trireg-variants
   carry no net_type field (variant identity IS the net_type fact);
   non-trireg variants carry the new NonTriregNetKind (11-way closed
   Disj of the §3.7.1 non-trireg keywords). Strength presence rides
   the existing Clause Disjs (DriveStrengthClause / new
   ChargeStrengthClause), not a top-level NetDeclaration axis. Per-form
   declarators split: NetAssignmentDeclarator (name + required
   rhs_lexeme) vs NetIdentifierDeclarator (name only). The unified
   NetDeclarator + NetInitializerClause types dissolved into this
   structural split.

   NetType refactored to {NonTriregNet { kind: NonTriregNetKind } |
   TriregNet} 2-way Disj — single source of truth for the §3.7.1
   keywords, no parallel/duplicated representation of the partition.
   ANSI port-net carriers (AnsiNetType / OutputAnsiNetType /
   AnsiInputInoutNet) continue to use `net_type: NetType` unchanged
   in shape; port-position §12.3.3 trireg-exclusion is a separate
   finding not in scope here.

2. NON-BLOCKING — VectoredessClause → VectorednessClause rename
   (field is already named `vectoredness`). Four occurrences updated.

3. NON-BLOCKING — shared NonEmptyList scaffold-note header text
   updated from "Six sites" to match the enumeration. NetDeclaration's
   former single non-empty site dissolves into the four per-variant
   list_of_net_decl_assignments / list_of_net_identifiers sites; the
   enumeration is now 14 entries (was 11). grep -c '🟡 spec-non-empty
   (§' invariant: 14 (verified).

The NonEmptyList deferral disposition is unchanged — the four new
per-variant sites ride the existing RQ-3 / std/collection.dag Wave-A2
`List<T> where non_empty` refinement deferral, NOT a verilog-local
NonEmptyList carrier mint. Same operator-pending dissolution trigger.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: address openai-pro 4-pack BLOCKING inline reviews on PR #3176 sha 1eb241a2

Four spec-right findings, all in-pattern declaration-class spec-
fidelity, fixed in one bundle:

1. PortConnections (§A.4.1.1) — added `NoPortConnections` nullary
   variant. The §A.4.1.1 grammar makes `[list_of_port_connections]`
   optional at module_instance, so `Adder a1 ();` (empty parens) is
   legal spec syntax. The prior 2-variant shape made this state
   representable two ways (positional-empty vs named-empty lists),
   violating P2 representation-duality. The 3-way Disj makes the
   empty-`()` form structurally distinct from non-empty ordered/
   named lists; the two inner lists (`actuals`, `connections`) ride
   the established RQ-3 / std/collection.dag Wave-A2 spec-non-empty
   deferral as new sites 15-16.

2. DefparamDeclaration / EventDeclaration / GenvarDeclaration
   (§A.2.5 / §A.2.1.4 / §A.2.1.1) — each refactored from singular-
   entry to non-empty list of per-entry sub-records mirroring the
   ParameterDeclaration / SpecparamDeclaration / LocalParameter
   Declaration / ModuleParameters pattern. New `DefparamAssignment`
   Conj sub-record for §A.2.5 list_of_defparam_assignments;
   `event_names: List<Symbol>` for §A.2.1.4 list_of_event_
   identifiers; `genvar_names: List<Symbol>` for §A.2.1.1 list_of_
   genvar_identifiers. Restores the spec statement-boundary
   (shared keyword across multi-entry forms) that the prior
   singular shape lost. New non-empty sites 17-19 in the shared
   scaffold note.

3. UdpInstantiation (§A.5.2) — refactored to the same shared-header
   + non-empty-instance-list pattern as ModuleInstantiation:
   shared (udp_name, drive_strength, delay) clause + non-empty
   List<UdpInstance> with per-instance (instance_name, body_lexeme).
   The prior singular-instance shape lost the §A.5.2 statement-
   boundary for `udp_identifier [drive_strength] [delay2]
   udp_instance { , udp_instance } ;`. Reuses the existing
   DriveStrengthClause / DelayClause Disjs (delay2-vs-delay3 sub-
   grammar distinction is a bundled-LanguageModel concern via the
   lexeme payload, not a new substrate Disj). New non-empty site 20.

4. VerilogModule (§A.1.2) — added `module_keyword: ModuleKeyword`
   to both NonAnsiVerilogModule and AnsiVerilogModule variants.
   New closed `ModuleKeyword` Disj { ModuleKw | MacromoduleKw }
   with full Practice-4 ledger; carries the §A.1.2 module-keyword
   distinction (module vs macromodule) that the prior shape
   collapsed before emission. parse ∘ emit now preserves which
   keyword the writer used (macromodule simulator hint can no
   longer silently flatten to module).

Shared NonEmptyList scaffold-note header count: "Fourteen" →
"Twenty"; enumeration: 14 → 20 entries; provenance addendum
documenting all four findings at sha 1eb241a2. grep -c '🟡 spec-
non-empty (§' invariant: 20 (verified).

All four inherit the established RQ-3 / std/collection.dag Wave-A2
`List<T> where non_empty` deferral; NO verilog-local NonEmptyList
mint. NonEmptyList + design-element deferrals unchanged.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: delete orphaned PortAnsiTypeKind per codex non-blocking improvement on PR #3176 sha 6f587e6c

PortAnsiTypeKind was the predecessor generic 6-variant ANSI-port
type/kind classifier. After the earlier direction-specific
AnsiPortDeclaration split landed (AnsiInputPort + AnsiInoutPort using
AnsiNetPortType for net-only; AnsiOutputPort using OutputPortAnsiTypeKind
for the §12.3.3 output-admissible subset), PortAnsiTypeKind had zero
field-position uses and existed only as a parallel-authority carrier
modeling the same ANSI-port type/kind space as the direction-specific
classifiers. Codex non-blocking improvement on PR #3176 sha 6f587e6c
flagged the parallel-authority risk; deletion is the resolution.

Deleted: the 84-line PortAnsiTypeKind type + ledger block.
Updated: OutputPortAnsiTypeKind ledger patterns 2 and 5 rewritten to
stand alone (no parent-set back-reference); AnsiPortDeclaration ledger
commentary updated to drop PortAnsiTypeKind / AnsiRegType / AnsiIntegerType
back-references.

grep -c '🟡 spec-non-empty (§' invariant: 20 (unchanged, this commit
is type-declaration cleanup only).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: address openai-pro 7-pack BLOCKING inline reviews on PR #3176 sha cba903a3e

Seven spec-right declaration-class spec-fidelity findings, all in-
pattern, fixed in one bundle:

1. VectorRange (§A.8.3) — msb/lsb scaffold reshape from Int-pair to
   lexeme-pair (msb_lexeme/lsb_lexeme: String). Per §A.8.3 range ::=
   [constant_expression : constant_expression], constant_expression
   admits constant-identifier references (e.g. WIDTH), arithmetic
   (WIDTH-1), conditional, etc. — the Int-pair shape collapsed
   spec-legal parameterized declarations like reg [WIDTH-1:0] into
   unrepresentable states. Lexeme follows the established
   body_lexeme/rhs_lexeme/default_lexeme precedent; dissolution
   trigger updated: bundled T-4 LanguageModel constant_expression
   productions parse the lexeme into an AST (the bounded-Cardinality
   refinement was wrong-shape because it couldn't capture
   parameterized expressions).

2. NetDeclaration vectoredness × range coupling (§A.2.1.3 / §3.7.1)
   — new NetVectoredPacking Disj couples vectoredness to range-
   presence structurally. Per §3.7.1: "The vectored keyword can be
   used only with a vector declaration." The prior independent
   vectoredness + packing fields admitted spec-illegal `wire
   vectored a;` (unranged-with-vectoredness); refactored all 4
   NetDeclaration variants to carry `net_packing: NetVectoredPacking
   = NetUnranged | NetRanged { vectoredness, range: VectorRange }`,
   making the illegal state unrepresentable.

3. PortDeclaration (§A.2.1.2) — singular-name → non-empty list-form
   mirroring the established Defparam/Event/Genvar pattern. `input
   a, b, c;` per §A.2.1.2 list_of_port_identifiers is one statement
   declaring multiple ports under a shared direction keyword; new
   site 21 in the spec-non-empty enumeration.

4. NamedParameterOverride (§A.4.1) — actual: String → actual:
   ParameterOverrideActual (new 2-way Disj {BlankParameterOverride |
   ParameterOverrideExpression{lexeme}}). Per §A.4.1: named_
   parameter_assignment ::= .parameter_identifier ( [mintypmax_
   expression] ); the optional brackets make `.PARAM()` (blank
   actual, retain default) legal spec syntax. Sibling Disj of
   PortConnectionActual.BlankConnection.

5. ModuleInstance (§A.4.1.1) — added instance_range:
   InstanceRangeClause field. Per §A.4.1.1 name_of_module_instance
   ::= module_instance_identifier [range]; instance arrays like
   `Adder a[7:0] (...)` were unrepresentable. New InstanceRangeClause
   Disj (NoInstanceRange | InstanceRange{range: VectorRange}) reused
   by ModuleInstance + UdpInstanceName.

6. UdpInstance (§A.5.2) — reshape to optional name+range via new
   UdpInstanceName Disj. Per §A.5.2 udp_instance ::=
   [name_of_udp_instance] ( ... ) with name_of_udp_instance ::=
   udp_instance_identifier [range]; unnamed UDP instances (`xor (o,
   a, b)`) and instance arrays were both unrepresentable. New
   UdpInstanceName Disj (NoUdpInstanceName | NamedUdpInstance{name,
   instance_range: InstanceRangeClause}) carries both spec-legal
   forms.

7. AnsiModuleItem + NonAnsiModuleItem (§A.1.4 / §A.9.1) — added
   attributes: AttributeInstanceClause first field on each variant
   payload. Per §A.1.4 most module_or_generate_items admit
   {attribute_instance} prefix (e.g. `(* keep *) assign x = y;`);
   the prior shape made attributes unrepresentable except via
   unrelated lexeme leaks. New closed AttributeInstanceClause Disj
   (NoAttributeInstances | AttributeInstanceLexeme{lexeme}) carried
   per-variant on 20 AnsiModuleItem variants + 2 NonAnsiModuleItem
   variants (NonAnsiAnsiCompatItem inherits via its wrapped
   AnsiModuleItem).

Shared NonEmptyList scaffold-note: "Twenty" → "Twenty-one" sites,
new site 21 (PortDeclaration.names) added with byte-identical
🟡 spec-non-empty marker. grep -c invariant: 21 (verified).
File-header scaffold-residual prose updated: VectorRange now
lexeme-pair-bridge to constant_expression sub-grammar, not raw-Int.

All deferrals continue under established RQ-3 / std/collection.dag
Wave-A2 disposition; NO verilog-local NonEmptyList carrier mint.
NonEmptyList + design-element + LanguageModel-spine deferral notes
intact.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* v4 T-4.9 verilog: address codex scheduled-review extensions on PR #3176 sha 51b9d49c

Codex scheduled review at sha 51b9d49c flagged 7 BLOCKINGs; 5 of 7
mapped 1:1 to the openai-pro inline BLOCKINGs already addressed in
HEAD 0d6d71454 (the 7-pack fix). The remaining 2 codex findings
extend scope on items I already touched:

1. Finding E ("instance naming ... reuse at module/UDP/gate
   boundaries"): module + UDP already reshaped in 0d6d71454. For
   gates, the per-gate-class shape matrix at §A.5.4 (cmos_switch
   forbids drive_strength but allows delay3; n_input/n_output admit
   delay2 not delay3; pass_switch forbids both; etc.) forbids a
   uniform structural per-instance carrier at the GateInstantiation
   level — a uniform carrier would re-introduce the admit-then-check
   anti-pattern on the gate-kind × clause-admissibility product.
   The per-instance name_of_gate_instance + range + per-class
   strength/delay structural extraction lives inside body_lexeme,
   riding the established UdpDefinition.body_lexeme / AlwaysBlock.
   body_lexeme sub-grammar deferral precedent. Updated
   GateInstantiation comment block to document the spec mapping
   explicitly + cite the §A.5.4 admissibility-matrix reason for the
   deferral.

2. Finding G ("attribute_instance at item/declaration/CONNECTION
   boundaries"): AnsiModuleItem + NonAnsiModuleItem item-boundaries
   already covered in 0d6d71454. Connection-boundary extension:
   - PortConnectionActual.ExpressionConnection gains
     `attributes: AttributeInstanceClause`
   - PortConnectionActual.BlankConnection gains
     `attributes: AttributeInstanceClause`
   - NamedPortConnection (Conj) gains
     `attributes: AttributeInstanceClause`
   Per §A.4.1.1 `named_port_connection ::= { attribute_instance } .
   port_identifier ( [expression] )` and `ordered_port_connection
   ::= { attribute_instance } [expression]` — both connection forms
   admit the prefix. Reuses the AttributeInstanceClause Disj
   introduced in 0d6d71454.

Findings A, B, C, D, F map 1:1 to openai-pro inlines already in
0d6d71454 — no new fixes needed.

NonEmptyList scaffold-note unchanged (no new list sites). grep -c
'🟡 spec-non-empty (§' invariant: 21 (unchanged).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: T-4.9 verilog

* v4 T-4.9 verilog: address openai-pro 5-pack on-HEAD verdict BLOCKINGs on PR #3176 sha 4ccc6267

openai-pro's first genuine on-HEAD verdict (4ccc6267) flagged 5
BLOCKINGs. All spec-right declaration-class spec-fidelity findings;
4 mechanical extensions + 1 self-correction of a 4ccc6267 regression:

1. AnsiPortDeclaration multi-name + attributes (§A.1.3) — all 3
   ANSI port direction variants reshape from single-name carriers
   to non-empty name lists with attribute-instance prefix:
   - AnsiInputPort/AnsiInoutPort: `List<Symbol>` per
     list_of_port_identifiers
   - AnsiOutputPort: `List<AnsiOutputPortDeclarator>` per
     list_of_variable_port_identifiers — output variable-ports admit
     per-port initializers via the existing VariableInitializerClause
   - All 3 variants gain `attributes: AttributeInstanceClause`
   The prior single-name-no-attributes shape dropped §A.1.3
   declaration-boundary facts (multi-identifier statement, attribute
   prefix). New AnsiOutputPortDeclarator Conj for the output-variant-
   specific per-port-initializer fact. Sites 22-24 in the spec-non-
   empty enumeration.

2. VariableDeclarator product → Disj split (§A.2.4) — prior
   `{name, unpacked_dimensions, initializer}` product admitted the
   spec-illegal `reg mem[0:1023] = 8'h00` combined state. Per spec
   `variable_type ::= identifier { dimension } | identifier =
   constant_expression` is mutually exclusive. Split into closed Disj
   `NamedVariable {name, unpacked_dimensions} | InitializedVariable
   {name, initializer_lexeme}` with full Practice-4 ledger; the
   InitializedVariable's lexeme is unconditional (not optional)
   since variant identity = initializer-present (no admit-then-check
   on a NoInitializer state).

3. NetIdentifierDeclarator + EventDeclaration per-identifier
   dimensions (§A.2.3 / §A.2.1.4) — both spec productions allow
   per-identifier `[ dimension { dimension } ]` suffix.
   NetIdentifierDeclarator gained `unpacked_dimensions:
   UnpackedDimensionsClaus…
briansrls added a commit that referenced this pull request May 18, 2026
4/4 lanes now ratified. T-4-mgr (vivid-carp-207) verified vs main:
T-29(#3267)/T-4.10(#3168)/T-4.12(#3171) already LANDED, not Wave-0 —
parallel count ≈14→≈11. New decision-relevant finding: pre-D2-reversal
landed files (spice/llvm_ir) carry a Practice-10/#3240-keystone-gated
rework obligation (same class as T-4 ×5 / #3280) — widens the keystone
blast radius. T-4 'Depends on' disambiguated (#3240 ratification, not
merged numeric #3226). T-29 residual #3277 attribution flagged open.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
briansrls added a commit that referenced this pull request May 18, 2026
…(discussion) (#3322)

* docs: R4 program dispatch plan — T-1..T-32 dependency chart + lane mapping

Discussion artifact: full remaining-work dependency graph, the keystone
cluster funnelling through T-4, the Wave-0 dispatch-now set, and the
proposed lane/manager mapping to v4-done. For operator + lane-manager
review ahead of program-wide fan-out.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold Lane A/B/Dissolution review corrections into R4 dispatch plan

Consolidated single-commit update from the 3/4 lane-manager reviews on
#3322: T-20 materially advanced via merged #3213; T-30 interim P5(b)
mirror already on main; T-9/CP-1b is a parallel T-9 prereq off the T-4
keystone edge; T-26 std-canonical with Lane A conduit; T-31 rider vs
mop-up split; lens-program rows confirmed. T-4-mgr rows pending explicit
ack (consistent with standing #3280 hold).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fold T-4-mgr review — staleness fixes + widened keystone scope

4/4 lanes now ratified. T-4-mgr (vivid-carp-207) verified vs main:
T-29(#3267)/T-4.10(#3168)/T-4.12(#3171) already LANDED, not Wave-0 —
parallel count ≈14→≈11. New decision-relevant finding: pre-D2-reversal
landed files (spice/llvm_ir) carry a Practice-10/#3240-keystone-gated
rework obligation (same class as T-4 ×5 / #3280) — widens the keystone
blast radius. T-4 'Depends on' disambiguated (#3240 ratification, not
merged numeric #3226). T-29 residual #3277 attribution flagged open.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix §5/§6 internal consistency vs folded corrections (Lane A finding)

Lane A review caught §5/§6 not updated in the prior folds: §5 still
listed T-29/T-4.10/T-4.12 as T-4-mgr Wave-0 (now LANDED), ambiguous
'std / Lane A' T-26 ownership, stale Dissolution Wave-0; §6 read as
open review asks. §5 now matches §2/§3/§4 (T-26 std-authoritative /
Lane A conduit; T-4-mgr Wave-0 empty; Dissolution T-31(b)/T-30
generated-checker); §6 → ratified status (4/4 lanes, operator §3 open).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fresh-lane structure (§5) + operator decision sheet (§7)

§5 → fresh composite manager lanes under witty-cat-59 (no reused
managers, per operator); two non-migrated exceptions (vivid-carp-207
= sole #3280 freeze custodian; fierce-cat-31 = lens-fan-out closeout).
§7 → consolidated decision sheet: the A-vs-B root ruling explained in
tradeoff terms + every pending blocking question (#3280 disposition,
#3240 ratification, T-25-core, Wave-0 go, fresh-lane defaults, de-prose
py removal, #3313) with recommendations.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix §1 ASCII keystone diagram vs §3 (cursor BLOCKING — T-29)

§1 graphic still drew T-29 inside the keystone box while §3/§2/§5
treat it as LANDED (#3267), not a keystone — same single-chart
internal-consistency class as the §5/§6 fix. Diagram now: 3-item
cluster (P1-KEYSTONE / T-25-core / T-30); T-29 shown LANDED below.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold #3313 lens-rework impact (Wave-2 taxonomy + batch-d hold)

#3313 is in active design rework (L1.6 retired→L1.10 family, A0/A1
umbrella, pre-Practice-10-ratification). §7 row 7 updated: it's no
longer flat L1.7–L1.12; Wave-2 batch (d) held track-not-finalize so
witnesses aren't authored against the moving taxonomy; batches a/b/c
and the keystone framing unaffected (#3313 reinforces #1=B/#3240).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: record operator B2 ruling on #3321 driver shape (§7 row 8)

Operator ruled 2026-05-18: substrate-native (B2). registry.dag splits
to its own .dag PR (lands now); the ~467-LOC tools/ Rust crate dropped
entirely, B1 also rejected — no interim out-of-substrate enforcement
shell (Python OR Rust), same thesis ruling as the de-prose-py kill.
Whole-corpus gate re-scoped to the v2 filesystem-walk substrate
primitive = the T-21/T-24 corpus-drive capability (PREFIX = first
consumer). Operator-accepted: CI lens gate lands when that lands.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fold still-hawk-102 review — keystone spec sharpness + 2-owner fix

(1) #3240 is a CLOSED/SUPERSEDED tracker, NOT ratifiable — the keystone
artifact is a not-yet-drafted modeling-discipline.md fold PR that
still-hawk-102 owns drafting; §7 #3a → "authorize draft", §3 rewritten.
(2) "one decision" overstated → "2-3 distinct operator items"; A-vs-B=B
stated as IMPLIED by the keystone-fold, not equivalent. (3) §5 two-owner
lens seam fixed: Fresh Compiler-Pipeline lens scope GATED on
fierce-cat-31 fan-out closeout (one lens owner; no P2 parallel-authority
drift). (4) §7 #2 no-revert-of-862bbde6e clause added. Self-consistency
pass: fixed 2 stale "ratify #3240" stragglers (§3 blast-radius, §6 r5).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold sunny-wolf-435 Wave-2 prereq + cross-lane edge (#3313 author)

#3313 author flagged two real Wave-2 sequencing gaps: (1) unenumerated
std/ prerequisite carriers the L1.x lenses read (canonical_observations,
CanonicalConcept, 3 Exemption registries) — T-25-core-class, no owning
T-# yet (P10-shape gap); (2) three derived lens-stages (match_arm_shape,
closed_vocab_scan, concept_home) = Compiler-Pipeline+Lens lane, NOT
Dissolution. Added §4 Wave-2-prereq block + cross-lane edge
(Compiler-Pipeline builds → Dissolution Wave-2 consumes); §5 Dissolution
row annotated. Reinforces batch-(d) hold.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: re-tee keystone ask to verified-exact (still-hawk self-correction)

still-hawk-102 verify-don't-trust'd its own review #1: the keystone
FOLD is ALREADY on main (modeling-discipline.md §581-763). Both prior
framings ('ratify #3240' and 'authorize a drafting effort') were wrong.
Corrected verified-exact: operator ratifies the verbatim invariant
blockquote at modeling-discipline.md ~§594-600 (exists, flagged
proposed/#3240-A1); still-hawk then lands it into INVARIANTS.md+
MODELING.md + de-hedges 3 sites — SMALL (~30-60 ln, mechanical, low-risk),
ratify-exact-text-today not a drafting effort. Downstream effort = the
retroactive v4 audit sweep (#3240 C1). §3(a)/§7#3a/§6r5/trailer aligned.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix last stale 'not-yet-drafted' straggler (§3 blast-radius)

* docs: keystone retraction (C1 not gated on A1) + Wave-2 prereq classification

(A) still-hawk-102 third self-correction, verified: #3241 (fold) + #3242
(🟡-legend) BOTH merged; the v4 audit sweep #3240-C1 was gated on #3242
(merged), NOT on the A1 invariant — C1 already in motion independently.
Retracted the 'authorizing A1 kicks off the v4 sweep' framing in
§3(a)/§7#3a: A1 ⇒ ONLY the small placement PR, maximally low-stakes.
(B) sunny-wolf-435 (#3313 author) classification, verified NONE fold
under T-25-core: (1a) canonical_observations/CanonicalConcept → NEW T-#
'lens-supporting concept registries'; (1b) 3 Exemption registries →
fold into each lens's own task, no T-#; (2) 3 derived lens-stages →
NEW shared T-# 'Wave-2-prereq lens-pipeline derivations'. Two new
owning-T#s to assign (P10-shape). §4 Wave-2-prereq block rewritten.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: final keystone re-tee — C1 sweep #3243 DONE (verified), A1 = sole open

* docs: rename live keystone gate → 'Practice-10 A1 invariant'; #3240 = closed-tracker only (cursor editorial)

* WIP: May 18

* docs: fix T-18 forward-dep violation (BLOCKING) + wave-ordering convention

Valid BLOCKING: §2 + TASKS.md say T-18 (coverage meta-lens) depends on
T-12/T-13 ('meta over the other lenses'), which only become real in
Wave 3 — yet §4 listed T-18 in Wave 2 (consumer before input = Facts-
Flow-Forward violation). Moved T-18 Wave 2 → Wave 4 (after T-12/T-13
real). Added a wave-ordering convention note: Wave = membership not
intra-wave sequence; §2 Depends-on orders within a wave; consumer-
before-input across waves is the real violation class.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: topological re-sort of wavefront (BLOCKING T-16 + pre-empt queued)

Operator BLOCKING review fired consumer-before-input findings (T-18,
T-16, and the same class T-4.8/T-17). Replaced the weak intra-wave
convention with a TOPOLOGICAL invariant (a task is strictly later than
every dep; within-wave = mutually independent, dispatch-safe on face)
and re-sorted: W2 drops T-4.8; W3 gains T-4.8; W4 gains T-17 (deps T-12
real W3) + T-18; W5 = T-16 (deps T-11 W4); W6 = T-15 terminal. Every
consumer now strictly after its fresh inputs.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: mirror §4 topological re-sort into §5 (codex BLOCKING residual)

codex BLOCKING (vs ed8b3b9, pre-resort) demanded T-18-after-T12/13,
T-16-after-T-11, AND 'mirror that gating in §5'. §4 was already fixed
by 9cd9831; the residual was §5 not mirroring it — the Compiler-
Pipeline 'Gated' cell was a flat 'post-T-4' bag obscuring the wave
sequence. Now §5 Compiler-Pipeline + Test/Bootstrap-Infra gated columns
explicitly mirror §4 topology (W2 T-9 → … → W5 T-16 → W6 T-15).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold L0/L1 asymmetry — Layer-0 hygiene CI gate early (max-utility-early)

sunny-wolf-435 (#3313 author), verified vs #3313 §4/§9/§10: Layer-0
(L0.1-L0.15) reads parse+resolve only (both LANDED), NO T-9 → CI
hygiene hard-gate goes live END-WAVE-1 once lens-pipeline-derivations
+ Layer-0 lens stage land. Layer-1 (L1.1-L1.12) needs post-T-9 +
concept registries → Wave-3. §4 W1 now carries the early Layer-0
gate; W3 the L1.x fan-out; batch-d hold unchanged for L1.x. Directly
serves the operator 'maximum utility as early as possible (without
compromising standards)' directive.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: restore T-29 as TASKS.md-declared T-4-cpp keystone feeder (codex RC)

codex REQUEST_CHANGES, VERIFIED vs origin/main: TASKS.md:64/:286/:1035
still declares T-29 a hard prerequisite of T-4's cpp slice
({P1-KEYSTONE,T-30,T-29,T-25-core}→T-4), and #3277 (T-29 residual) is
OPEN — only #3267 (core) merged. The prior "T-29 LANDED / not a
keystone / removed from critical branch" reclassification was a real
P2/Practice-9 documentation-authority violation (dispatch graph
disagreeing with the source of truth → could mis-sequence T-4). T-29
restored to the keystone cluster across §1 graph, §2 row, §3 table,
§4 wave note, §5 extdeps/T-4, §6 review-status; de-classify only when
#3277 lands AND TASKS.md updates (authority = TASKS.md, not this plan).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: §7 #3b — T-25-core is authorize-to-build (ratified Category-6 shape), not an open design fork

---------

Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
briansrls added a commit that referenced this pull request May 19, 2026
* docs: R4 program dispatch plan — T-1..T-32 dependency chart + lane mapping

Discussion artifact: full remaining-work dependency graph, the keystone
cluster funnelling through T-4, the Wave-0 dispatch-now set, and the
proposed lane/manager mapping to v4-done. For operator + lane-manager
review ahead of program-wide fan-out.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold Lane A/B/Dissolution review corrections into R4 dispatch plan

Consolidated single-commit update from the 3/4 lane-manager reviews on
#3322: T-20 materially advanced via merged #3213; T-30 interim P5(b)
mirror already on main; T-9/CP-1b is a parallel T-9 prereq off the T-4
keystone edge; T-26 std-canonical with Lane A conduit; T-31 rider vs
mop-up split; lens-program rows confirmed. T-4-mgr rows pending explicit
ack (consistent with standing #3280 hold).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fold T-4-mgr review — staleness fixes + widened keystone scope

4/4 lanes now ratified. T-4-mgr (vivid-carp-207) verified vs main:
T-29(#3267)/T-4.10(#3168)/T-4.12(#3171) already LANDED, not Wave-0 —
parallel count ≈14→≈11. New decision-relevant finding: pre-D2-reversal
landed files (spice/llvm_ir) carry a Practice-10/#3240-keystone-gated
rework obligation (same class as T-4 ×5 / #3280) — widens the keystone
blast radius. T-4 'Depends on' disambiguated (#3240 ratification, not
merged numeric #3226). T-29 residual #3277 attribution flagged open.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix §5/§6 internal consistency vs folded corrections (Lane A finding)

Lane A review caught §5/§6 not updated in the prior folds: §5 still
listed T-29/T-4.10/T-4.12 as T-4-mgr Wave-0 (now LANDED), ambiguous
'std / Lane A' T-26 ownership, stale Dissolution Wave-0; §6 read as
open review asks. §5 now matches §2/§3/§4 (T-26 std-authoritative /
Lane A conduit; T-4-mgr Wave-0 empty; Dissolution T-31(b)/T-30
generated-checker); §6 → ratified status (4/4 lanes, operator §3 open).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fresh-lane structure (§5) + operator decision sheet (§7)

§5 → fresh composite manager lanes under witty-cat-59 (no reused
managers, per operator); two non-migrated exceptions (vivid-carp-207
= sole #3280 freeze custodian; fierce-cat-31 = lens-fan-out closeout).
§7 → consolidated decision sheet: the A-vs-B root ruling explained in
tradeoff terms + every pending blocking question (#3280 disposition,
#3240 ratification, T-25-core, Wave-0 go, fresh-lane defaults, de-prose
py removal, #3313) with recommendations.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix §1 ASCII keystone diagram vs §3 (cursor BLOCKING — T-29)

§1 graphic still drew T-29 inside the keystone box while §3/§2/§5
treat it as LANDED (#3267), not a keystone — same single-chart
internal-consistency class as the §5/§6 fix. Diagram now: 3-item
cluster (P1-KEYSTONE / T-25-core / T-30); T-29 shown LANDED below.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold #3313 lens-rework impact (Wave-2 taxonomy + batch-d hold)

#3313 is in active design rework (L1.6 retired→L1.10 family, A0/A1
umbrella, pre-Practice-10-ratification). §7 row 7 updated: it's no
longer flat L1.7–L1.12; Wave-2 batch (d) held track-not-finalize so
witnesses aren't authored against the moving taxonomy; batches a/b/c
and the keystone framing unaffected (#3313 reinforces #1=B/#3240).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: record operator B2 ruling on #3321 driver shape (§7 row 8)

Operator ruled 2026-05-18: substrate-native (B2). registry.dag splits
to its own .dag PR (lands now); the ~467-LOC tools/ Rust crate dropped
entirely, B1 also rejected — no interim out-of-substrate enforcement
shell (Python OR Rust), same thesis ruling as the de-prose-py kill.
Whole-corpus gate re-scoped to the v2 filesystem-walk substrate
primitive = the T-21/T-24 corpus-drive capability (PREFIX = first
consumer). Operator-accepted: CI lens gate lands when that lands.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fold still-hawk-102 review — keystone spec sharpness + 2-owner fix

(1) #3240 is a CLOSED/SUPERSEDED tracker, NOT ratifiable — the keystone
artifact is a not-yet-drafted modeling-discipline.md fold PR that
still-hawk-102 owns drafting; §7 #3a → "authorize draft", §3 rewritten.
(2) "one decision" overstated → "2-3 distinct operator items"; A-vs-B=B
stated as IMPLIED by the keystone-fold, not equivalent. (3) §5 two-owner
lens seam fixed: Fresh Compiler-Pipeline lens scope GATED on
fierce-cat-31 fan-out closeout (one lens owner; no P2 parallel-authority
drift). (4) §7 #2 no-revert-of-862bbde6e clause added. Self-consistency
pass: fixed 2 stale "ratify #3240" stragglers (§3 blast-radius, §6 r5).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold sunny-wolf-435 Wave-2 prereq + cross-lane edge (#3313 author)

#3313 author flagged two real Wave-2 sequencing gaps: (1) unenumerated
std/ prerequisite carriers the L1.x lenses read (canonical_observations,
CanonicalConcept, 3 Exemption registries) — T-25-core-class, no owning
T-# yet (P10-shape gap); (2) three derived lens-stages (match_arm_shape,
closed_vocab_scan, concept_home) = Compiler-Pipeline+Lens lane, NOT
Dissolution. Added §4 Wave-2-prereq block + cross-lane edge
(Compiler-Pipeline builds → Dissolution Wave-2 consumes); §5 Dissolution
row annotated. Reinforces batch-(d) hold.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: re-tee keystone ask to verified-exact (still-hawk self-correction)

still-hawk-102 verify-don't-trust'd its own review #1: the keystone
FOLD is ALREADY on main (modeling-discipline.md §581-763). Both prior
framings ('ratify #3240' and 'authorize a drafting effort') were wrong.
Corrected verified-exact: operator ratifies the verbatim invariant
blockquote at modeling-discipline.md ~§594-600 (exists, flagged
proposed/#3240-A1); still-hawk then lands it into INVARIANTS.md+
MODELING.md + de-hedges 3 sites — SMALL (~30-60 ln, mechanical, low-risk),
ratify-exact-text-today not a drafting effort. Downstream effort = the
retroactive v4 audit sweep (#3240 C1). §3(a)/§7#3a/§6r5/trailer aligned.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fix last stale 'not-yet-drafted' straggler (§3 blast-radius)

* docs: keystone retraction (C1 not gated on A1) + Wave-2 prereq classification

(A) still-hawk-102 third self-correction, verified: #3241 (fold) + #3242
(🟡-legend) BOTH merged; the v4 audit sweep #3240-C1 was gated on #3242
(merged), NOT on the A1 invariant — C1 already in motion independently.
Retracted the 'authorizing A1 kicks off the v4 sweep' framing in
§3(a)/§7#3a: A1 ⇒ ONLY the small placement PR, maximally low-stakes.
(B) sunny-wolf-435 (#3313 author) classification, verified NONE fold
under T-25-core: (1a) canonical_observations/CanonicalConcept → NEW T-#
'lens-supporting concept registries'; (1b) 3 Exemption registries →
fold into each lens's own task, no T-#; (2) 3 derived lens-stages →
NEW shared T-# 'Wave-2-prereq lens-pipeline derivations'. Two new
owning-T#s to assign (P10-shape). §4 Wave-2-prereq block rewritten.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: final keystone re-tee — C1 sweep #3243 DONE (verified), A1 = sole open

* docs: rename live keystone gate → 'Practice-10 A1 invariant'; #3240 = closed-tracker only (cursor editorial)

* WIP: May 18

* docs: fix T-18 forward-dep violation (BLOCKING) + wave-ordering convention

Valid BLOCKING: §2 + TASKS.md say T-18 (coverage meta-lens) depends on
T-12/T-13 ('meta over the other lenses'), which only become real in
Wave 3 — yet §4 listed T-18 in Wave 2 (consumer before input = Facts-
Flow-Forward violation). Moved T-18 Wave 2 → Wave 4 (after T-12/T-13
real). Added a wave-ordering convention note: Wave = membership not
intra-wave sequence; §2 Depends-on orders within a wave; consumer-
before-input across waves is the real violation class.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: topological re-sort of wavefront (BLOCKING T-16 + pre-empt queued)

Operator BLOCKING review fired consumer-before-input findings (T-18,
T-16, and the same class T-4.8/T-17). Replaced the weak intra-wave
convention with a TOPOLOGICAL invariant (a task is strictly later than
every dep; within-wave = mutually independent, dispatch-safe on face)
and re-sorted: W2 drops T-4.8; W3 gains T-4.8; W4 gains T-17 (deps T-12
real W3) + T-18; W5 = T-16 (deps T-11 W4); W6 = T-15 terminal. Every
consumer now strictly after its fresh inputs.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: mirror §4 topological re-sort into §5 (codex BLOCKING residual)

codex BLOCKING (vs ed8b3b9, pre-resort) demanded T-18-after-T12/13,
T-16-after-T-11, AND 'mirror that gating in §5'. §4 was already fixed
by 9cd9831; the residual was §5 not mirroring it — the Compiler-
Pipeline 'Gated' cell was a flat 'post-T-4' bag obscuring the wave
sequence. Now §5 Compiler-Pipeline + Test/Bootstrap-Infra gated columns
explicitly mirror §4 topology (W2 T-9 → … → W5 T-16 → W6 T-15).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: fold L0/L1 asymmetry — Layer-0 hygiene CI gate early (max-utility-early)

sunny-wolf-435 (#3313 author), verified vs #3313 §4/§9/§10: Layer-0
(L0.1-L0.15) reads parse+resolve only (both LANDED), NO T-9 → CI
hygiene hard-gate goes live END-WAVE-1 once lens-pipeline-derivations
+ Layer-0 lens stage land. Layer-1 (L1.1-L1.12) needs post-T-9 +
concept registries → Wave-3. §4 W1 now carries the early Layer-0
gate; W3 the L1.x fan-out; batch-d hold unchanged for L1.x. Directly
serves the operator 'maximum utility as early as possible (without
compromising standards)' directive.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: restore T-29 as TASKS.md-declared T-4-cpp keystone feeder (codex RC)

codex REQUEST_CHANGES, VERIFIED vs origin/main: TASKS.md:64/:286/:1035
still declares T-29 a hard prerequisite of T-4's cpp slice
({P1-KEYSTONE,T-30,T-29,T-25-core}→T-4), and #3277 (T-29 residual) is
OPEN — only #3267 (core) merged. The prior "T-29 LANDED / not a
keystone / removed from critical branch" reclassification was a real
P2/Practice-9 documentation-authority violation (dispatch graph
disagreeing with the source of truth → could mis-sequence T-4). T-29
restored to the keystone cluster across §1 graph, §2 row, §3 table,
§4 wave note, §5 extdeps/T-4, §6 review-status; de-classify only when
#3277 lands AND TASKS.md updates (authority = TASKS.md, not this plan).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: §7 #3b — T-25-core is authorize-to-build (ratified Category-6 shape), not an open design fork

* docs: reconcile T-25-core framing class to §7 #3b ratified authorize-to-build shape

Blocking operator review on #3339 (r4-program-dispatch-plan.md): T-25-core
was still framed as an open design-direction / operator-review fork in §2,
§3, and the §6/§7 prose, contradicting §7 #3b (commit 363bb76) and the
canonical authority (TASKS.md:940-943 operator-ratified; :962-982 +
coercion-design.md Category 6 = shape already designed: base type +
fail-closed validation at a named constructor boundary). Fixed the whole
class (lines 108, 151, 201-202, 206, 345, 392-393, 396) to "authorize-to-
build stamp, shape ratified, NOT a design fork". Legit keystone-cluster
feeder references (TASKS.md:64 exact set) left intact — canonically correct.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* WIP: May 18

* docs: fix dual-authority — §5 lane active-status + §6 row carried "HELD on keystone" shorthand vs the full feeder set (openai-pro RC #3339)

openai-pro REQUEST_CHANGES (review 14421, head b2f0fa5): §5 Fresh
extdeps/T-4 lane active-status cell (:317) and §6 vivid-carp-207 row
(:341) still said "HELD on keystone", contradicting §2 :81 "all four
gate T-4" + the same row's gated cell. A worker scanning the lane table
could read keystone-closure as sufficient. Both now state the full
TASKS.md:286 feeder set {P1-KEYSTONE,T-30,T-29,T-25-core} — one gate
everywhere. Same class as the prior 3-site normalization; this closes
the active-status shorthand the earlier pass missed.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: add TASKS.md anchor convention note (cursor #3339 exploratory obs — APPROVE)

cursor/composer-2 (review 14425) APPROVE, no findings; one actionable
exploratory observation: the brief cites `TASKS.md:NNN` without a path
and there is no root-level `TASKS.md` (only src/v4/TASKS.md), so a reader
could hunt for a missing file. Added one proportionate anchor-convention
note to the Purpose block (not churning every citation) stating all
`TASKS.md:NNN` anchors refer to src/v4/TASKS.md.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: Wave 1 over-gated T-4.5/T-4.6 on the full ×4 — split unblock conditions (openai-pro RC #3339, review 14429)

Valid finding (a regression from the prior Wave 1 normalization): grouping
"T-4 ×5 languages, T-4.5, T-4.6 unblock" under "the keystone-cluster ×4
land" implied T-4.5/T-4.6 are gated on the full {P1-KEYSTONE,T-30,T-29,
T-25-core}. But §2 :85/:86 declare T-4.5 deps {T-3,T-25-core} and T-4.6
deps {T-25-core,T-26} — neither needs P1-KEYSTONE/T-30/T-29. Wave 1 text
now gates only T-4 ×5 on the full ×4; T-4.5/T-4.6 unblock on T-25-core
(their sole cluster feeder) + own §2 deps, potentially earlier. §2 table
reaffirmed as the dependency authority.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: whole-doc §1/§4/§5-vs-§2 consistency sweep — harden §5 gated cell (T-4.5–4.8 not full-×4); pre-empt the recurring class

Following the openai-pro 14429 Wave-1 over-gating fix (f223fb7), did a
full consistency audit of every gate/unblock restatement vs the §2
dependency authority. §4 Waves 2-6, §1 ASCII, §6 verified consistent.
One latent ambiguity remained: §5 extdeps/T-4 gated cell listed
"T-4.5–4.8" right after "T-4 (post the full feeder set)", readable as
T-4.5–4.8 being full-×4-gated. Hardened it to state T-4.5–4.8 follow
their own §2 deps (not the full ×4) + §2 is the sole dependency
authority — closing the class that successive reviews kept finding one
instance of, rather than waiting for the next gap-by-gap flag.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* docs: drop brittle internal :NN self-anchors → name-only refs (openai-pro RC #3339, review 14436)

Valid finding: §5 lane row self-referenced "§2 T-4 row :81" but the doc
grew from prior edits so :81 is now T-6 (T-4 is :84). Root cause is
hardcoded internal line anchors that re-stale on every edit. Per
openai-pro's own "remove the numeric suffix" option, converted ALL
internal self-anchors to name-based refs: §5 ":81" dropped; Wave 1
"§2 :85/:86" → "per the §2 T-4.5/T-4.6 row". External src/v4/TASKS.md:NN
anchors untouched (different stable file). Permanently closes the
brittle-self-anchor sub-class rather than chasing the number each pass.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

---------

Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@briansrls
briansrls deleted the session/snappy-badger-570 branch June 1, 2026 18:43
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant