Group racing accesses into disjoint components

[sim642]

Accesses of a single location are grouped into disjoint components, i.e. connected components in the graph of accesses with may_race edges).
This doesn't strictly improve precision, because all the same accesses are still printed, but it improves the precision and usability of the output by making it clearer, which accesses cannot race with which.
It makes sense to expose this information because the pairwise race checking internally knows (only previously only implicitly).

Example

In the added test tests/regression/10-synch/05-two_unique_two_lock.c.

Before

All accesses are printed under one warning.

[Warning][Race] Memory location myglobal@05-two_unique_two_lock.c:5:5-5:13 (race with conf. 110):
  write with [lock:{A}, thread * mhp:(([f1@tests/regression/10-synch/05-two_unique_two_lock.c:31:3-31:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:11:3-11:13)
  write with [lock:{B}, thread * mhp:(([f1@tests/regression/10-synch/05-two_unique_two_lock.c:31:3-31:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:14:3-14:13)
  write with [lock:{A}, thread * mhp:(([f2@tests/regression/10-synch/05-two_unique_two_lock.c:32:3-32:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:21:3-21:13)
  write with [lock:{B}, thread * mhp:(([f2@tests/regression/10-synch/05-two_unique_two_lock.c:32:3-32:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:24:3-24:13)

After

Accesses are printed under two different warnings for the same location such that the two racing components have no races between each other, only internally:

[Warning][Race] Memory location myglobal@05-two_unique_two_lock.c:5:5-5:13 (race with conf. 110):
  write with [lock:{B}, thread * mhp:(([f1@tests/regression/10-synch/05-two_unique_two_lock.c:31:3-31:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:14:3-14:13)
  write with [lock:{A}, thread * mhp:(([f2@tests/regression/10-synch/05-two_unique_two_lock.c:32:3-32:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:21:3-21:13)

[Warning][Race] Memory location myglobal@05-two_unique_two_lock.c:5:5-5:13 (race with conf. 110):
  write with [lock:{A}, thread * mhp:(([f1@tests/regression/10-synch/05-two_unique_two_lock.c:31:3-31:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:11:3-11:13)
  write with [lock:{B}, thread * mhp:(([f2@tests/regression/10-synch/05-two_unique_two_lock.c:32:3-32:37, main], {}), ...)] (conf. 110)  (exp: & myglobal) (tests/regression/10-synch/05-two_unique_two_lock.c:24:3-24:13)