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feat(cake_rmsnorm): opt-in non-deterministic weight gradient for the autograd RMSNorm - #8208
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yyihuang merged 1 commit intoNov 1, 2026
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…r the training RMSNorm The names the training RMSNorm had before the deterministic package took its det names (flashinfer.cake_rmsnorm_train, cake_rmsnorm, CakeRMSNormFunction, the forward / backward / workspace entry points) become a package of their own. Every entry point takes deterministic (default True): True returns the deterministic package's results; False runs this package's backward, which selects per token-count window a single-kernel form (FP64 dw column sums; twosum per-thread sums in the windows the backward's notes name) or the deterministic package's backward pair rendered into this package. dx is the same bit for bit across calls; dw is not bitwise reproducible. In every backward window the dw stays within 0.85 of the per-element budget (atol 1e-4 + rtol 1e-4 against FP64 at the kernel's FP32 rstd, worst of 60 inputs of each of three input families, BF16 and FP32 weight) up to T 65536, and no worse than the FP32 eager reference where that reference errs less. On H = 5120 the pair windows run the deterministic package's plain and compensated programs at its own switch row counts (6144 / 5120 / 19968 on SM100 / SM103 / SM107) up to T 65536 (57344 for the FP32 weight on SM107); the single kernel runs above. Package, facade, tests, benchmark and docs. Window edges and shared-memory wait levels are measured on B200, GB300 and R200.
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@flashinfer-bot run tests/norm/test_cake_rmsnorm_train.py tests/norm/test_cake_rmsnorm_train_api.py tests/norm/test_cake_rmsnorm_train_pairs.py tests/norm/test_cake_rmsnorm_train_windows.py tests/norm/test_cake_rmsnorm_train_vendored.py |
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@flashinfer-bot run tests/norm/test_cake_rmsnorm_train_legacy.py tests/norm/test_cake_rmsnorm_train_ckpt.py tests/norm/test_cake_rmsnorm_train_stall.py tests/norm/test_cake_rmsnorm_train_all_sm.py tests/norm/test_cake_rmsnorm_train_dist.py tests/norm/test_cake_rmsnorm_det_train_aliases.py |
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- @yzh119 -> docs/api/norm.rst
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- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fcbfa14d591a9babfd26_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd08c6f436eb6071fa22_binding.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd08c6f436eb6071fa22_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd1097c45c1e328871fd_binding.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd1097c45c1e328871fd_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd913ecd254a6bba4b18_binding.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fd913ecd254a6bba4b18_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fdfa500c83d95df0f5c1_binding.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fdfa500c83d95df0f5c1_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fef03ce50a792c8704bd_binding.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/csrc/cake_rmsnorm_train_fef03ce50a792c8704bd_kernel.cu
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/.gitignore
- @yzh119 -> flashinfer/cake_rmsnorm_train_backend/init.py
- @yzh119 -> flashinfer/cake_rmsnorm_train.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_det_train_aliases.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_all_sm.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_api.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_ckpt.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_dist.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_legacy.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_pairs.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_stall.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_vendored.py
- @yzh119 -> tests/norm/test_cake_rmsnorm_train_windows.py
The following files match only the catch-all rule; this approval covers that technical gap under the one-approval policy. GitHub still requires each owned path's own owner.
- benchmarks/bench_cake_rmsnorm_train.py
- flashinfer/init.py
- .github/labeler.yml
- .pre-commit-config.yaml
- pyproject.toml
- scripts/check_cake_build_manifests.py
- tests/test_helpers/cake_package.py
- tests/test_helpers/cake_rmsnorm_train_reference.py
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… and moves backward windows for dw accuracy Follow-up to flashinfer-ai#8208 for the opt-in non-deterministic weight gradient (deterministic=False) of flashinfer.cake_rmsnorm_train. Forward: on every architecture, route and token count the package now runs the program the deterministic package selects (its programs and windows rendered into this package), so y, rstd and the residual output are bitwise equal to deterministic=True. In flashinfer-ai#8208 the H = 256 routes and, on SM100 and SM103, the H = 5120 routes ran forward windows and programs that differ from the deterministic package's. Why the backward windows move: in flashinfer-ai#8208 dw elements of four routed deterministic pairs exceed the per-element budget at sampled token counts: SM103 H = 4096 at T 50688 (1.032 of the budget) and the FP32-weight H = 6144 route at T 56320 (1.010; 1.085 at T 54273 against FP64 at torch's FP32 rstd), and on a 212-SM R200 the FP32-weight H = 6144 route at T 31040 (1.057) and the FP32-weight H = 1536 route at T 61952 (1.020). Seven more routed pair windows reach more than 0.85 of the budget: SM100 H = 2048 (0.883 at T 59392), H = 4096 (0.923 at T 52737) and its FP32-weight route (0.916 at T 65024; 0.983 at T 63488 against FP64 at torch's FP32 rstd), SM103 the FP32-weight H = 2048 (0.904 at T 62464) and H = 5120 (0.888 at T 62464) routes, SM107 H = 1536 (0.980 at T 62976) and H = 6144 (0.978 at T 31232). On a 212-SM R200 the worst dw error of three FP32-weight pairs exceeds the FP32 eager reduction's: H = 512 at T 1088, 1664, 1920 and 2368, H = 4096 at T 24576 (0.7328 against 0.7241) and H = 6144 at T 30784 and 31040. Backward windows: the single kernel (FP64 dw column sums; twosum per-thread sums on SM103) now runs above - SM100: T 58880 on H = 2048 and T 52736 on H = 4096; - SM103: T 49152 on H = 6144, T 61952 on H = 5120 and H = 2048, T 46592 on BF16-weight H = 1536 and T 50176 on BF16-weight H = 4096, and from 114688 to 139264 rows on H = 256 (the twosum form); - SM107: T 30720 on H = 6144, T 53248 on H = 1536 and T 24064 on FP32-weight H = 4096; FP32-weight H = 512 runs it above T 1024 up to T 4096. Each move covers both weight dtypes unless a weight is named: the BF16- and FP32-weight deterministic pairs compute the same dw for equal inputs, so a failing input of one is a failing input of the other. SM103 H = 2048 (its twosum form) and SM107 H = 1536 get new single kernel programs, builds of the same kernel source; SM107 FP32-weight H = 512 and SM103 H = 256 get new instances of existing single kernel programs. Cost: the single kernel's median backward time against the pair it replaces (B200 and GB300 per timing session, R200 over two sessions): SM100 (B200) 1.001-1.009x on H = 2048 (T 58881 to 65536), 1.009-1.050x on H = 4096 (T 52737 to 65536), 0.995-1.020x on FP32-weight H = 4096 (T 59905 to 65536); SM103 (GB300) 1.022-1.033x on H = 4096 (T 50176 to 63488), 1.071-1.080x on FP32-weight H = 6144 (T 49152 to 60416), 1.173-1.182x on FP32-weight H = 5120 (T 61952 to 65536); SM107 (R200, 212 SMs) 1.558-1.598x on H = 6144 (T 31744), 1.433-1.478x on H = 1536 (T 57344 to 65536), 1.379-1.414x on FP32-weight H = 512 (T 1088 to 4096), 1.349-1.373x on FP32-weight H = 4096 (T 24576 to 28672). Not yet timed (measurement at this head in progress): SM100 FP32-weight H = 2048 (T 58881 to 65536) and FP32-weight H = 4096 (T 52737 to 59904); SM103 H = 6144 BF16 (T 49153 to 51200), BF16 H = 1536 (T 46593 to 53248), BF16 H = 5120 (T 61953 to 65536), H = 2048 both weights (T 61953 to 65536); SM103 H = 256 both weights (114689 to 139264 rows); SM107 216 SMs. Backward, SM107 H = 5120 (both weight dtypes): the deterministic package's compensated pair now runs from T 19968 up to T 49152 and the FP64-accumulating single kernel above it. In flashinfer-ai#8208 the pair ran up to T 65536 (BF16 weight) and T 57344 (FP32 weight). On a 212-SM R200 one BF16-weight dw element of that pair exceeds the budget at T 61440 (1.110 of it); on a 216-SM R200 its worst element reaches 0.867 of the budget at T 53248 and 0.891 at T 61440 with BF16 weight, and 0.905 at T 57344 with FP32 weight. Above T 49152 the single kernels stay within 0.703 (BF16 weight) and 0.646 (FP32 weight) of the budget at the sampled token counts up to 65537. Their median backward time is 1.34-1.39x the pair's on 216 SMs and 1.80-1.87x on 212 SMs (T 53248 to 65536). Backward, SM103 H = 256 (both weight dtypes): above 5120 rows the deterministic package's pairs run in that package's own windows and programs instead of this package's single kernels, except from 114688 to 139264 rows, where the twosum single kernel runs: there the deterministic pair's worst dw element reaches 0.9475 of the budget at 126976 rows and 0.8692 at 122880 rows with BF16 weight and 0.9362 at 135168 rows with FP32 weight (worst of 200 inputs of each of three families). The pairs' median backward time is 0.829-0.972x that of the kernels they replace on GB300, and their worst dw element stays within 0.837 of the budget at the sampled row counts where they run. Up to 5120 rows nothing changes. Accuracy of dw with deterministic=False, against FP64 at the kernel's FP32 rstd with the per-element budget atol 1e-4 + rtol 1e-4, worst over 60 or more inputs of each of three input families, BF16 and FP32 weight, at every sampled token count up to 65536: the bounds of the deterministic pairs and single kernels at this head are being measured and will be stated here. The median dw error over the inputs of each family is no worse than the FP32 eager reduction's at every sampled token count, except one family of the SM103 FP32-weight H = 512 route at T 1088 (0.0395 against 0.0376). On the H = 5120, per-head H = 256 and FP32-weight routes the worst dw error over all sampled inputs is also no worse than the FP32 eager reduction's at every sampled token count; the moved ranges and the 216-SM R200 are being confirmed. The registry comments and the H = 5120 test comment state measured values; the docstrings say that deterministic=True reproduces dw bitwise for a given token count on devices with the same SM count.
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…#8253) Follow-up to #8208 for the opt-in non-deterministic weight gradient (deterministic=False) of flashinfer.cake_rmsnorm_train. Forward: on every architecture, route and token count the package now runs the program the deterministic package selects (its programs and windows rendered into this package), so y, rstd and the residual output are bitwise equal to deterministic=True. In #8208 the H = 256 routes and, on SM100 and SM103, the H = 5120 routes ran forward windows and programs that differ from the deterministic package's. Why the backward windows move: in #8208 dw elements of five routed deterministic pairs besides the SM107 H = 5120 pair (below) exceed the per-element budget (atol 1e-4 + rtol 1e-4 against FP64 at the kernel's FP32 rstd) at sampled token counts up to 65536: on GB300 (SM103) H = 4096 at T 50688 (1.032 of the budget) and the FP32-weight H = 6144 route at T 56320 (1.010; 1.085 at T 54273 against FP64 at torch's FP32 rstd), and on a 212-SM R200 (SM107) both H = 6144 routes at T 31040 (1.057) and the FP32-weight H = 1536 route at T 61952 (1.020). Up to T 65536, six more routed pair windows reach more than 0.85 of the budget with inputs of their own weight dtype: on B200 (SM100) H = 2048 (0.883 at T 59392), H = 4096 (0.923 at T 52737) and its FP32-weight route (0.909 at T 44544 and 0.916 at T 65024; 0.983 at T 63488 against FP64 at torch's FP32 rstd), on GB300 the FP32-weight H = 2048 (0.904 at T 62464) and H = 5120 (0.888 at T 62464) routes, and on a 212-SM R200 H = 1536 (0.980 at T 62976). On a 212-SM R200 the BF16-weight form of the FP32-weight H = 2048 pair, the same dw computation, reaches 0.900 of the budget at T 51200 (0.873 at T 55296 on a 216-SM R200), and on GB300 the FP32-weight form of the BF16-weight H = 1536 pair, the same dw computation, reaches 0.890 at T 47104. The worst dw error of seven FP32-weight pairs exceeds the FP32 eager reduction's: on a 212-SM R200 H = 512 at T 1088, 1664, 1920 and 2368, H = 4096 at T 24576 (0.7328 against 0.7241), H = 6144 at T 30784 (0.8671 against 0.8066) and H = 256 at 2048 rows (512 tokens of 4 heads; 0.1435 against 0.1158), on B200 H = 1536 at T 33280 (0.6840 against 0.6219), and on GB300 H = 1536 at T 38400 (0.7399 against 0.7092) and H = 4096 at T 9728 (0.3383 against 0.3332). On a 216-SM R200 the worst dw error of the SM107 FP32-weight H = 6144 pair exceeds the eager reduction's at T 29184 (0.8224 against 0.8121), and that of the SM107 FP32-weight H = 4096 pair that ran from T 1 to 256 at T 64 (0.0256 against 0.0233). On a 212-SM R200 the median dw error of that H = 4096 pair also exceeds the eager reduction's at T 4 (0.0024 against 0.0022), and its worst at T 8 and 16 (0.0079 against 0.0078 and 0.0109 against 0.0106) and, on the input family for which the BF16-weight H = 4096 pair computes the same dw (measured with that pair), at T 5, 6, 9 and 20 (0.0043 against 0.0037, 0.0063 against 0.0049, 0.0071 against 0.0070 and 0.0119 against 0.0108). Backward windows: the single kernel (FP64 dw column sums; twosum per-thread sums on SM103 and on SM107 FP32-weight H = 2048) now runs above - SM100: T 58880 on H = 2048, T 44032 on H = 4096 and T 32768 on FP32-weight H = 1536; - SM103: T 49152 on H = 6144, T 61952 on H = 5120 and H = 2048, T 46592 on BF16-weight and T 37888 on FP32-weight H = 1536, and T 50176 on BF16-weight and T 9216 on FP32-weight H = 4096; - SM107: T 30720 on BF16-weight and T 28672 on FP32-weight H = 6144, T 53248 on H = 1536, T 24064 on FP32-weight H = 4096, T 50176 on FP32-weight H = 2048 (where the BF16-weight route already ends) and 1536 rows on FP32-weight H = 256; FP32-weight H = 512 runs it above T 1024 up to T 4096, and FP32-weight H = 4096 also from T 1 to 256 (the single kernel of that route's top window). Each move covers both weight dtypes unless a weight is named: the BF16- and FP32-weight deterministic pairs compute the same dw for equal inputs, so a failing input of one is a failing input of the other. A worst error above the FP32 eager reduction's (read on the FP32-weight, H = 5120 and H = 256 routes) moves only the route on which it occurs. SM103 H = 2048 (its twosum form) and SM107 H = 1536 get new single kernel programs, builds of the same kernel sources; SM107 FP32-weight H = 512 runs a single kernel program this package ships for SM100, now also built for SM107; the other moved windows run single kernel programs this package already ships for their architecture. The main kernels of the SM100 FP32-weight H = 1536 pair that ran from T 32768 to 36864 and of the SM107 FP32-weight H = 4096 pair that ran from T 1 to 256 are no longer shipped. Small token counts: a survey of the routed programs of every backward route whose lowest window ran a deterministic pair in #8208, other than the SM107 FP32-weight H = 4096 route (above), at every T from 1 to 64 and T 96, 127 to 129, 192, 255 and 256 on B200, GB300 and a 212-SM R200, and on the R200 also at every T up to 256 on H = 512, H = 2048 and H = 256 ([T, 256] input), with 60 inputs of each of three families and more token counts sampled near and above each cut, finds on all 35 of these routes that the pair's median dw error over all inputs, or on the FP32-weight, H = 5120 and H = 256 routes also its worst dw error, exceeds the FP32 eager reduction's at some sampled T (on four of them only at T 3 and by less than 0.0001 of the budget). On every one of these routes a single kernel now runs from T 1 up to a cut and the pair above it: the single kernel is no worse than the eager reduction by those readings at every sampled T up to the cut, and the pair at every sampled T above it (on SM103 FP32-weight H = 1536, over the 60 inputs of each family, the pair's worst dw error exceeds the eager reduction's at T 320, 0.0596 against 0.0583 of the budget, so its cut is 320). On 31 of these routes the single kernel is one that the route also runs in a higher window (on 9 of them the twosum form). On FP32-weight H = 512 of SM100 and SM103 no single kernel the route ran passes there (SM103 ran none): over the 60 inputs of each family an FP64-accumulating single kernel of the same tiling, on SM100 the one that route runs above T 960, exceeds the eager reduction's worst dw error at T 4 (0.0033 against 0.0032), so they run a twosum single kernel, new programs; on BF16-weight H = 512 SM103 and SM107 ran no single kernel, and they run an FP64-accumulating one, a new program on SM103 and on SM107 the program this package runs on SM100 H = 512. The cuts (in tokens; in rows on H = 256; each cut is set for its weight dtype alone): - SM100: BF16 weight 14 on H = 1536 and 26 on H = 512; FP32 weight 64 on H = 1536, 22 on H = 5120 and 292 on H = 512; - SM103: BF16 weight 14 on H = 1536, 12 on H = 2048, 1080 rows on H = 256, 22 on H = 5120, 26 on H = 512 and 3 on H = 4096 and H = 6144; FP32 weight 320 on H = 1536, 42 on H = 2048, 1080 rows on H = 256, 15 on H = 4096, 22 on H = 5120, 20 on H = 6144, 6 on residual H = 6144 and 292 on H = 512; - SM107: BF16 weight 14 on H = 1536, 6 on H = 2048, 1056 rows on H = 256, 6 on H = 4096, 18 on H = 5120, 77 on H = 512 and 3 on H = 6144 and residual H = 6144; FP32 weight 64 on H = 1536, 127 on H = 2048, 1296 rows on H = 256, 229 on H = 512, 13 on H = 5120, 20 on H = 6144 and 3 on residual H = 6144. Cost: the single kernel's median backward time against the deterministic pair it replaces, over the timing sessions and their pooled medians (CUDA graph, L2 flushed before every replay): - B200 (148 SMs): 1.001-1.012x on H = 2048 and 0.997-1.005x on FP32-weight H = 2048 (T 58881 to 65536); 0.983-1.064x on H = 4096 and 0.980-1.043x on FP32-weight H = 4096 (T 44033 to 65536); 0.941-0.965x on FP32-weight H = 1536 (T 32769 to 36864); - GB300 (152 SMs): 1.297-1.311x on BF16-weight H = 1536 (T 46593 to 53248) and 1.322-1.336x on FP32-weight H = 1536 (T 37889 to 45056); 1.118-1.137x on H = 2048 and 1.183-1.200x on FP32-weight H = 2048 (T 61953 to 65536); 1.019-1.034x on BF16-weight H = 4096 (T 50177 to 63488) and 1.013-1.093x on FP32-weight H = 4096 (T 9217 to 23552); 1.136-1.154x on H = 5120 and 1.167-1.183x on FP32-weight H = 5120 (T 61953 to 65536); 1.051-1.061x on H = 6144 (T 49153 to 51200) and 1.062-1.079x on FP32-weight H = 6144 (T 49153 to 60416); - R200 (212 SMs): 1.586-1.600x on H = 6144 (T 30721 to 31744) and 1.543-1.566x on FP32-weight H = 6144 (T 30721 to 31744; T 28673 to 30720 not timed); 1.406-1.463x on H = 1536 and 1.415-1.478x on FP32-weight H = 1536 (T 53249 to 65536); 1.340-1.385x on FP32-weight H = 4096 (T 24576 to 28672; T 1 to 256 not timed), 1.313-1.423x on FP32-weight H = 512 (T 1088 to 4096), 1.233-1.267x on FP32-weight H = 2048 (T 50688 to 56320) and 1.102-1.165x on FP32-weight H = 256 (1537 to 3584 rows). Small-T cost: the single kernel's median backward time against the deterministic pair's in each of two timing sessions, and on GB300 also over the samples of both sessions (CUDA graph, L2 flushed before every replay, memory clock checked at the board maximum), at T 1, 4, 8 and 16 where those are at most the cut and at the cut (on H = 256 also at the cut in the 4-head and 24-head views; on the T 3 cuts at T 1 to 3): - B200 (148 SMs): 1.205-1.367x on H = 1536 and 0.952-1.150x on H = 512; with FP32 weight 1.157-1.304x on H = 1536, 1.044-1.132x on H = 512 and 1.610-1.872x on H = 5120. - GB300 (152 SMs): 1.889-2.088x on H = 1536, 1.890-2.105x on H = 2048, 1.014-1.276x on H = 256, 2.672-32.000x on H = 5120, 1.493-1.657x on H = 512, 2.502-2.592x on H = 4096 and 12.004-35.083x on H = 6144 (six sessions on three GPUs); with FP32 weight 1.904-2.019x on H = 1536 at T 1, 4, 8, 16 and 64 (four sessions at T 1 to 16) and 2.494-2.563x at T 320, 1.941-2.224x on H = 2048, 0.995-1.286x on H = 256, 1.929-2.139x on H = 512, 2.416-2.590x on H = 4096, 2.636-2.805x on H = 5120, 2.844-32.895x on H = 6144 and 6.149-34.422x on residual H = 6144. The largest ratios are at T 1, where the single kernels take 174.640 us (H = 5120), 212.128 to 212.353 us (H = 6144, session medians), 209.503 us (FP32-weight H = 6144) and 207.376 us (FP32-weight residual H = 6144) against 5.872, 6.048 to 6.336, 6.464 and 6.144 us for the pairs; the median time of every timed single kernel is at most 0.22 ms. - R200: not timed. Backward, SM107 H = 5120 (both weight dtypes): the compensated deterministic pair that #8208 runs from T 19968 now runs up to T 49152 and the FP64-accumulating single kernel above it. In #8208 the pair ran up to T 65536 (BF16 weight) and T 57344 (FP32 weight). On a 212-SM R200 one BF16-weight dw element of that pair exceeds the budget at T 61440 (1.110 of it); on a 216-SM R200 its worst element reaches 0.867 of the budget at T 53248 and 0.891 at T 61440 with BF16 weight, and 0.905 at T 57344 with FP32 weight (worst of 200 inputs of each of three families). Above T 49152 the single kernels stay within 0.703 (BF16 weight) and 0.646 (FP32 weight) of the budget at the sampled token counts up to 65537. Their median backward time is 1.80-1.87x the pair's on a 212-SM R200 (T 53248 to 65536). Since #8251 the deterministic package runs other programs on SM107 H = 5120 from T 19968, so from T 19968 to 49152 deterministic=True and deterministic=False run different deterministic pairs. Backward, SM103 H = 256 (both weight dtypes): above 5120 rows each row count runs a deterministic pair instead of this package's single kernels, except from 93184 to 139264 rows, where the twosum single kernel of #8208 keeps running. The pair's main kernel is the one the deterministic package runs for that row count on a device with 152 or more SMs; its dw reduce is that package's up to 40960 rows and above 1572864 rows, and from 40960 to 93184 and from 139264 to 1572864 rows the one that package ran there before #8319 (the measured pairs). From #8293 to #8319 the deterministic package ran the pair of 40960 to 93184 rows up to 99840 rows; that pair reaches 0.9807 of the budget at 93696 rows (3904 tokens of 24 heads, FP32 weight, worst of 60 inputs of each of three families). In that time it ran another pair from 99840 rows, whose worst dw element stays within 0.353 (BF16 weight) and 0.373 (FP32 weight) of the budget at the sampled row counts up to 139264 rows (worst of 200 inputs of each of three families); this package keeps the twosum single kernel up to 139264 rows. From 139264 to 1572864 rows, where this package now runs that pair in place of the twosum single kernel, the twosum single kernel's median backward time on GB300 is 1.058-1.095x (1.060-1.093x pooled) that pair's at every timed row count; below 139264 rows the two are not timed against each other. Where the pairs run, their worst dw element stays within 0.837 of the budget at every sampled row count, and on GB300 their median backward time is 0.820-0.989x (0.829-0.972x pooled) that of the single kernels they replace. From 93184 to 139264 rows the twosum single kernel's median backward time is 1.130-1.188x that of the pair of 40960 to 93184 rows on GB300. Up to 1080 rows the single kernel runs (small token counts, above); from 1081 to 5120 rows nothing changes. Accuracy of dw with deterministic=False at this head, against FP64 at the kernel's FP32 rstd and at torch's FP32 rstd with the per-element budget atol 1e-4 + rtol 1e-4, worst over 60 or more inputs of each of three input families, BF16 and FP32 weight, at every sampled token count up to 65536, the top of the qualified range (every sampled row count of the H = 256 views): the routed deterministic pairs stay within 0.850 of the budget (B200 0.842; GB300 0.850; R200 0.832 with 212 SMs and 0.844 with 216 SMs) and the single kernels within 0.751 (B200 0.713; GB300 0.572, the twosum forms 0.0006; R200 0.727 with 212 SMs and 0.751 with 216 SMs). Over the same samples the median dw error over the inputs is no worse than the FP32 eager reduction's at every sampled token count where both were recorded; above T 256 the median over the inputs of each family is no worse either, except one family of the SM103 FP32-weight H = 512 route at T 1088 (0.0395 against 0.0376). On the H = 5120, H = 256 and FP32-weight routes the worst dw error over those inputs is also no worse than the FP32 eager reduction's at every sampled token count on B200, GB300 and R200 (212 and 216 SMs). The window tables record the measured outcome at each of the 74 new backward edges (10 on SM100, 37 on SM103 and 27 on SM107; dx is bitwise identical across every one) and, for each of the 130 new backward windows (19, 64 and 47), the smallest side allocation (100 or 132 KB per CTA) beside which it waits for a kernel resident on every SM, or that it waits beside neither, measured on B200, GB300 and a 212-SM R200. Beside 100 KB per CTA the SM103 H = 6144 single kernels above T 49152 wait, where the pairs they replace waited from 132 KB. Other new windows that wait beside a smaller allocation than the program that ran their token counts in #8208: SM100 bwd_w32_h5120 (0, 22]; SM103 none; SM107 none. The registry's window-reason comments state measured values, except the two SM100 H = 5120 comments above T 65536, which name the top of the qualified range; the H = 5120 test comment states measured values. The window notes name the small-T windows and the twosum windows from T 1. The docstrings say that deterministic=True reproduces dw bitwise for a given token count on devices with the same SM count. The mixed-form workspace test in test_cake_rmsnorm_train_pairs.py takes the first BF16-weight route without residual of SM100, SM103 or SM107 whose window at 257 tokens runs the deterministic pair, and discounts the route's own single-kernel records up to 256 tokens: no route runs the deterministic pair at 1 token now.
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Nov 4, 2026
… and run the deterministic pair in two GB300 backward windows (#8577) Related issue: https://github.com/flashinfer-ai/flashinfer/issues/8066 `flashinfer.cake_rmsnorm_train` is RMSNorm for training. The forward returns y (BF16) and rstd (FP32), and the backward returns dx (BF16) and dw (FP32). The two modes, `deterministic=True` and `deterministic=False`, use the same forward and differ only in the backward. The family ships for sm_100a (B200), sm_103a (GB300) and sm_107a (R200). The tables cover these forms in both modes: - [T, H] rows with BF16 weight (H512 to H6144) - FP32 weight (`w32`): H5120 and H6144, plus H2048 and H4096 in the B200 small-T rows - fused residual add (`res`, H6144) with BF16 or FP32 weight - per-head views [T,24,256] (strided) and [T,4,256] (contiguous), with a shared w[256] This follow-up to #8208 and #8253 changes only the `deterministic=False` backward. It makes two changes: - Column-task launch (all three GPUs): the column-task programs (H2048, H4096, H5120, H6144, the `res` H6144 route and their FP32-weight twins) now launch one CTA per row chunk plus one per column task, capped at the slot count, as the deterministic column-task programs already do; the grid changes only at small T, where a few CTAs used to run every column task in turn. - Two GB300 windows: at H6144 from T449 to T1152 (both weight dtypes) and at H5120 (BF16 weight) from T321 to T896, the backward now runs the deterministic pair instead of its single kernel, because the pair is faster there (the pair is the main kernel + fixed-order dw reduce, programs the package already ships). Speedup = baseline latency / new latency. A value > 1 means the new kernel is faster. Geomeans over the 78-shape list, vs deterministic / vs SOTA: - fwd (same forward in both modes): B200 1.001x / 1.015x, GB300 1.001x / 1.017x, R200 0.999x / 1.012x - bwd: B200 1.048x / 1.157x, GB300 0.991x / 1.146x, R200 0.942x / 1.080x - 2xfwd+bwd: B200 1.022x / 1.120x, GB300 0.998x / 1.138x, R200 0.971x / 1.096x The B200 vs-SOTA geomeans leave out the two B200 `!` rows. Added rows, vs deterministic / vs SOTA (small T = T1, T4, T16 and T64): - B200 small-T (36): fwd 1.003x / 0.940x, bwd 1.537x / 1.029x, 2xfwd+bwd 1.220x / 0.999x - GB300 small-T (20): fwd 1.000x / 0.888x, bwd 1.173x / 1.055x, 2xfwd+bwd 1.073x / 1.195x - GB300 window rows (9): fwd 0.999x / 1.026x, bwd 0.971x / 1.219x, 2xfwd+bwd 0.998x / 1.242x - R200 small-T (8): fwd 0.994x / 0.903x, bwd 1.005x / 0.758x, 2xfwd+bwd 0.991x / 0.884x Notable rows: - Small T vs deterministic: B200 small-T bwd runs at 1.26x to 1.76x, and all 36 rows are faster. GB300 small-T bwd reaches 1.46x (geomean 1.173). R200 small-T rows are at parity (bwd 0.983x to 1.019x). - In a separate earlier run on B200 and GB300, T = 1 backward took 87-212 us with the previous non-deterministic programs and 3.8-4.5 us with this PR's programs. - torch.compile still beats the new kernel at T = 1 backward on all three GPUs. The exception is GB300 `res` and `res w32`. Example, B200 H2048 T1 bwd: det 5.98 us, SOTA 2.08 us (tcd), new 3.87 us. On R200, SOTA is faster on all 8 small-T bwd rows (0.518x to 0.936x vs SOTA). - The rows below are slower than deterministic. This is pre-existing: this PR does not change their GPU programs or launch. Latencies are new vs det: - R200 at large T. The lowest is H5120 T65536 bwd at 300.86 vs 161.73 us (0.54x). Others: H6144 T32768 bwd 162.40 vs 101.82 us (0.63x) and H6144 T65536 bwd 311.11 vs 192.77 us (0.62x). The full list is every R200 row below 0.95x vs det. - GB300: H1536 T65536 bwd 128.45 vs 101.47 us (0.79x); [T,4,256] T1024 bwd 9.70 vs 7.94 us (0.82x); H5120 T65536 and H5120 T65536 w32 bwd 0.85x to 0.87x; H6144 T64 res bwd 8.03 vs 7.36 us (0.92x). - B200: [T,24,256] T65536 bwd 427.77 vs 384.89 us (0.90x, `!`). - GB300 window rows: both modes launch the same GPU programs here. The new mode measures 0.962x to 0.996x of det on bwd (geomean 0.971). This gap comes from the timing order (see below), not from the GPU programs. Baselines and measurement. Every row has two baselines: - det: the deterministic Cake kernel (`deterministic=True`). Its GPU programs are those of FlashInfer main at a1b4ed39. This PR does not touch the deterministic package. - SOTA: per row, the fastest non-Cake candidate that has the same outputs (BF16 y / dx / h_new, FP32 rstd / dw) and meets the accuracy budget. This is the strongest applicable comparison: every listed candidate is timed on every row, and the fastest in-budget one is taken. APIs that return dw in the weight dtype (Liger, QuACK, TE) do not have matched outputs and are never chosen. Apex FusedRMSNorm has no wheel. new = the non-deterministic Cake kernel of this PR (`deterministic=False`). The accuracy budget takes the worst of 5 seeds: y and dx atol = rtol = 1e-2; rstd rel. error <= 1e-4; dw per element atol 1e-4 + rtol 1e-4 vs FP64. New and det meet it on every row on all three GPUs. Latency = median of 804 CUPTI spans per implementation per row. One span is one CUDA-graph replay after an L2 flush (cold L2). It includes the implementation's own setup, reduction, cast and copy kernels. For each GPU type, 4 sessions ran in parallel on 4 GPUs of one node (2 in row order, 2 in reverse). Each session ran 3 interleaved passes x 67 replays. eps = 1e-6. Latencies print to 0.01 us and per-row ratios to 0.01x. In each session the implementations run in a fixed order: det first, then the non-Cake candidates, then new. A later check on B200 and GB300 found that this order alone moves an implementation's latency by up to about 5 %: rows where both modes launch the same GPU programs read 0.95x to 1.05x instead of 1.00x. A ratio within about 5 % of 1.00x is therefore not a measured difference. All implementations of a row run in one process that also loads every non-Cake candidate, including torch.compile. A later check found that loading torch.compile into the process makes the Cake kernels faster on small rows (B200 H1536 T1024: bwd 8.40 to 7.45 us, fwd 3.33 to 2.61 us; GB300 H6144 T449: bwd about 10.9 to 9.70 us, fwd about 4.1 to 3.15 us), while the non-Cake candidates gain about 3.5-5 %. On small rows the ratios vs SOTA can therefore overstate the new kernel's lead; the size per row is being measured. Ratios vs det are not affected (both are Cake kernels in the same process). Key: - Shapes: H = hidden size, T = tokens. x / y / dx are BF16, rstd / dw are FP32, and w is BF16 unless marked `w32`. `res` adds the BF16 output h_new. `[T,24,256]` has strides (12288, 512, 1), and `[T,4,256]` is contiguous. Both share w[256]. - SOTA: - tc = torch.compile of an explicit FP32-statistics reference (torch 2.14.1+cu130, inductor max-autotune-no-cudagraphs, static shape, emulate_precision_casts=True) - tcd = the same in torch.compile default mode - q = QuACK 0.6.5 heuristic config - qa = QuACK 0.6.5 exhaustive per-shape autotune (rmsnorm_fwd_tuned / rmsnorm_bwd_tuned, cached before timing) - on `res` rows, QuACK is torch add + QuACK - lg = Liger-Kernel 0.8.5 (Triton 3.8.0, casting_mode gemma) - Transformer Engine 2.20.2 was never fastest. PyTorch's fused rms_norm cannot run this form (BF16 x with FP32 w). - `~`: for det, SOTA or new, (max - min) / min of the 4 session medians is above 5.0 % (compared at 0.1 % resolution). - `*`: a faster non-Cake candidate fails the dw budget. These candidates are listed below the table. - `!`: no matched candidate meets the dw budget. The fastest matched one is shown, and the row is left out of the vs-SOTA summary. **B200 (sm_100a)** B200, 148 SMs, sm_100a, compute capability 10.0, driver 580.82.07, CUDA 13.4 (nvcc cuda_13.4.r13.4/compiler.38855100_0), torch 2.14.1+cu130. SM clock median 1965 MHz (99 % of samples at max), memory clock 3996 MHz, 4 GPUs of one node, no foreign GPU processes. Rows: 78 shapes + 36 small-T shapes, x 3 ops = 342 rows. The small-T shapes are T1, T4, T16 and T64 of H2048, H2048 w32, H4096, H4096 w32, H5120, H6144, H6144 w32, H6144 res and H6144 res w32. New and det meet the budget on every row. No matched candidate meets it on the 2 `!` rows. 39 rows were re-timed in a second run on another B200 node with the same software, because tc did not run on them in the first run: H1536 T65536, plus T256/T1024/T4096 of H5120 w32, H6144 w32, H6144 res and H6144 res w32. All columns of those rows come from the second run. - `~`: 117 rows - `!`: 2 rows, [T,24,256] T65536 bwd and 2xfwd+bwd. The fastest matched candidate is shown (tc, dw err/tol 1.122). | op | geomean vs det [min, max] | rows < 1 | geomean vs SOTA [min, max] | rows < 1 | | --- | --- | --- | --- | --- | | fwd (78) | 1.001x [0.974, 1.039] | 29 | 1.015x [0.908, 1.266] | 34 | | bwd (78) | 1.048x [0.900, 1.322] | 20 | 1.157x [0.977, 1.625] | 7 | | 2xfwd+bwd (78) | 1.022x [0.955, 1.135] | 23 | 1.120x [0.996, 1.386] | 1 | | fwd (small-T 36) | 1.003x [0.983, 1.034] | 6 | 0.940x [0.807, 1.147] | 26 | | bwd (small-T 36) | 1.537x [1.259, 1.758] | 0 | 1.029x [0.525, 1.533] | 13 | | 2xfwd+bwd (small-T 36) | 1.220x [1.070, 1.311] | 0 | 0.999x [0.755, 1.240] | 14 | The vs-SOTA columns leave out the `!` rows. | workload / shape / dtype / mode | operation | deterministic Cake latency (us) | non-Cake SOTA latency (us) | new non-deterministic Cake latency (us) | speedup vs deterministic Cake | speedup vs non-Cake SOTA | |---|---|---|---|---|---|---| |H512 T256|fwd~|2.24|2.11 tcd|2.21|1.01x|0.96x| |H512 T256|bwd~|5.60|6.56 tc|5.57|1.01x|1.18x| |H512 T256|step~|9.38|10.53 tc|9.41|1.00x|1.12x| |H512 T1024|fwd|2.53|2.46 tc|2.53|1.00x|0.97x| |H512 T1024|bwd|6.02|7.46 tc|6.02|1.00x|1.24x| |H512 T1024|step~|10.18|11.62 tc|10.27|0.99x|1.13x| |H512 T4096|fwd|3.55|3.52 tc|3.58|0.99x|0.98x| |H512 T4096|bwd~|9.74|10.78 tc|8.48|1.15x|1.27x| |H512 T4096|step|15.49|16.54 tc|13.98|1.11x|1.18x| |H512 T14928|fwd|7.07|7.01 q|7.26|0.97x|0.96x| |H512 T14928|bwd|16.00|24.29 qa|14.94|1.07x|1.63x| |H512 T14928|step|26.91|36.42 q|26.27|1.02x|1.39x| |H512 T16384|fwd|7.62|7.49 tcd|7.52|1.01x|1.00x| |H512 T16384|bwd|16.13|24.19 tc|15.81|1.02x|1.53x| |H512 T16384|step|27.74|36.77 tc|27.90|0.99x|1.32x| |H512 T32768|fwd|13.02|12.35 tcd|12.99|1.00x|0.95x| |H512 T32768|bwd|24.13|33.25 tc|24.13|1.00x|1.38x| |H512 T32768|step|45.57|55.49 tc|46.62|0.98x|1.19x| |H512 T65536|fwd|23.20|22.37 tcd|23.17|1.00x|0.97x| |H512 T65536|bwd|40.96|50.85 tc|40.45|1.01x|1.26x| |H512 T65536|step|84.13|91.23 tc|83.74|1.00x|1.09x| |H1536 T256|fwd|2.05|1.99 lg|2.05|1.00x|0.97x| |H1536 T256|bwd~|5.92|6.85 tc|6.05|0.98x|1.13x| |H1536 T256|step|9.73|10.59 tc|9.76|1.00x|1.09x| |H1536 T1024|fwd|2.59|2.75 q|2.59|1.00x|1.06x| |H1536 T1024|bwd~|7.36|9.25 tc|7.78|0.95x|1.19x| |H1536 T1024|step~|12.00|14.46 tc|12.51|0.96x|1.16x| |H1536 T4096|fwd~|5.02|5.31 tc|4.99|1.01x|1.06x| |H1536 T4096|bwd|13.22|17.54 tc|13.15|1.00x|1.33x| |H1536 T4096|step~|20.67|26.21 tc|20.93|0.99x|1.25x| |H1536 T14928|fwd|13.28|14.91 q|13.31|1.00x|1.12x| |H1536 T14928|bwd|28.54|37.82 tc|28.54|1.00x|1.33x| |H1536 T14928|step|51.84|67.06 qa|51.74|1.00x|1.30x| |H1536 T16384|fwd|14.46|16.10 q|14.59|0.99x|1.10x| |H1536 T16384|bwd|30.40|42.18 tc|30.27|1.00x|1.39x| |H1536 T16384|step|55.74|72.22 qa|55.74|1.00x|1.30x| |H1536 T32768|fwd|29.18|31.49 qa|29.15|1.00x|1.08x| |H1536 T32768|bwd|54.43|68.16 qa|54.21|1.00x|1.26x| |H1536 T32768|step|115.76|130.59 qa|110.94|1.04x|1.18x| |H1536 T65536|fwd|57.66|61.31 qa|57.38|1.01x|1.07x| |H1536 T65536|bwd|103.17|113.06 qa|101.69|1.01x|1.11x| |H1536 T65536|step|219.77|233.82 qa|215.55|1.02x|1.08x| |H2048 T1|fwd~|1.76|1.82 lg|1.76|1.00x|1.04x| |H2048 T1|bwd~|5.98|2.08 tcd|3.87|1.55x|0.54x| |H2048 T1|step~|9.06|6.05 tcd|7.46|1.21x|0.81x| |H2048 T4|fwd~|1.86|1.73 lg|1.86|1.00x|0.93x| |H2048 T4|bwd~|6.43|3.74 tc|3.97|1.62x|0.94x| |H2048 T4|step~|9.86|7.30 tc|7.87|1.25x|0.93x| |H2048 T16|fwd~|1.86|1.79 lg|1.86|1.00x|0.97x| |H2048 T16|bwd~|6.21|3.87 tc|3.87|1.60x|1.00x| |H2048 T16|step~|9.57|7.84 tc|7.30|1.31x|1.07x| |H2048 T64|fwd|1.92|1.82 lg|1.92|1.00x|0.95x| |H2048 T64|bwd~|6.34|4.96 tcd|3.90|1.62x|1.27x| |H2048 T64|step|9.06|7.78 tc|7.14|1.27x|1.09x| |H2048 T256|fwd|2.11|2.08 lg|2.11|1.00x|0.98x| |H2048 T256|bwd~|6.66|6.53 tc|5.15|1.29x|1.27x| |H2048 T256|step|10.18|11.26 tc|9.41|1.08x|1.20x| |H2048 T1024|fwd|2.75|2.91 tc|2.75|1.00x|1.06x| |H2048 T1024|bwd~|8.70|8.64 tc|8.48|1.03x|1.02x| |H2048 T1024|step|12.99|13.38 tc|13.02|1.00x|1.03x| |H2048 T4096|fwd~|5.98|6.02 tc|5.98|1.00x|1.01x| |H2048 T4096|bwd|17.95|19.33 tc|18.05|0.99x|1.07x| |H2048 T4096|step|28.32|29.22 tc|28.25|1.00x|1.03x| |H2048 T14928|fwd|17.82|18.40 q|17.63|1.01x|1.04x| |H2048 T14928|bwd|37.66|49.25 tc|36.50|1.03x|1.35x| |H2048 T14928|step|72.13|86.97 qa|68.38|1.05x|1.27x| |H2048 T16384|fwd|19.36|19.87 q|19.14|1.01x|1.04x| |H2048 T16384|bwd|40.51|52.73 qa|39.04|1.04x|1.35x| |H2048 T16384|step|78.30|94.21 qa|74.50|1.05x|1.26x| |H2048 T32768|fwd|38.83|39.36 q|38.85|1.00x|1.01x| |H2048 T32768|bwd|72.70|83.49 qa|71.14|1.02x|1.17x| |H2048 T32768|step|150.11|164.73 qa|144.64|1.04x|1.14x| |H2048 T65536|fwd|76.42|77.09 q|76.13|1.00x|1.01x| |H2048 T65536|bwd|133.79|143.21 qa|134.66|0.99x|1.06x| |H2048 T65536|step|286.56|299.68 qa|282.11|1.02x|1.06x| |H4096 T1|fwd~|2.16|2.21 lg|2.14|1.01x|1.03x| |H4096 T1|bwd~|5.57|2.85 tc|3.74|1.49x|0.76x| |H4096 T1|step~|8.61|5.98 tcd|7.07|1.22x|0.85x| |H4096 T4|fwd~|1.98|2.02 lg|1.95|1.02x|1.03x| |H4096 T4|bwd~|5.41|3.71 tcd|3.84|1.41x|0.97x| |H4096 T4|step~|8.67|7.02 tcd|7.10|1.22x|0.99x| |H4096 T16|fwd|1.98|2.02 lg|1.98|1.00x|1.02x| |H4096 T16|bwd~|5.89|4.45 tcd|3.97|1.48x|1.12x| |H4096 T16|step~|10.14|8.22 tcd|7.94|1.28x|1.04x| |H4096 T64|fwd|2.05|2.05 lg|2.05|1.00x|1.00x| |H4096 T64|bwd~|6.30|4.74 tcd|4.42|1.43x|1.07x| |H4096 T64|step~|9.95|8.58 tc|8.51|1.17x|1.01x| |H4096 T256|fwd|2.40|2.37 lg|2.42|0.99x|0.98x| |H4096 T256|bwd~|6.75|7.76 tc|6.66|1.01x|1.17x| |H4096 T256|step|10.59|12.02 tc|10.21|1.04x|1.18x| |H4096 T1024|fwd|3.65|4.13 qa|3.74|0.97x|1.10x| |H4096 T1024|bwd|11.07|11.49 tc|10.78|1.03x|1.07x| |H4096 T1024|step|16.96|18.24 tc|16.70|1.02x|1.09x| |H4096 T4096|fwd|9.60|11.04 qa|9.60|1.00x|1.15x| |H4096 T4096|bwd~|24.19|28.70 qa|24.29|1.00x|1.18x| |H4096 T4096|step|42.78|49.47 qa|42.78|1.00x|1.16x| |H4096 T14928|fwd|35.62|36.06 qa|35.36|1.01x|1.02x| |H4096 T14928|bwd|69.57|68.19 qa|65.73|1.06x|1.04x| |H4096 T14928|step|141.15|141.53 qa|132.13|1.07x|1.07x| |H4096 T16384|fwd~|38.61|39.55 qa|38.78|1.00x|1.02x| |H4096 T16384|bwd|74.59|73.82 qa|70.30|1.06x|1.05x| |H4096 T16384|step|152.00|154.30 qa|143.94|1.06x|1.07x| |H4096 T32768|fwd|76.34|77.44 qa|76.70|1.00x|1.01x| |H4096 T32768|bwd|134.62|132.29 qa|132.32|1.02x|1.00x| |H4096 T32768|step|285.82|287.21 qa|280.51|1.02x|1.02x| |H4096 T65536|fwd|154.62|156.70 qa|154.17|1.00x|1.02x| |H4096 T65536|bwd|252.38|262.11 tc|258.80|0.98x|1.01x| |H4096 T65536|step|554.05|570.68 tc|565.10|0.98x|1.01x| |H5120 T1|fwd~|2.37|2.18 lg|2.37|1.00x|0.92x| |H5120 T1|bwd~|6.05|2.75 tc|3.94|1.54x|0.70x| |H5120 T1|step~|9.74|6.72 tc|8.13|1.20x|0.83x| |H5120 T4|fwd~|2.18|2.05 lg|2.21|0.99x|0.93x| |H5120 T4|bwd~|5.70|4.35 tcd|3.84|1.48x|1.13x| |H5120 T4|step~|9.15|7.74 tcd|7.65|1.20x|1.01x| |H5120 T16|fwd~|2.18|2.08 lg|2.18|1.00x|0.96x| |H5120 T16|bwd|5.73|4.67 tc|3.90|1.47x|1.20x| |H5120 T16|step~|9.44|8.19 tcd|7.39|1.28x|1.11x| |H5120 T64|fwd|2.21|2.14 lg|2.24|0.99x|0.96x| |H5120 T64|bwd|6.11|5.25 tc|4.00|1.53x|1.31x| |H5120 T64|step|9.47|8.83 tc|7.74|1.22x|1.14x| |H5120 T256|fwd|2.69|2.72 lg|2.69|1.00x|1.01x| |H5120 T256|bwd~|7.42|9.07 tcd|7.04|1.05x|1.29x| |H5120 T256|step|11.33|13.73 tcd|11.26|1.01x|1.22x| |H5120 T1024|fwd|4.32|4.54 tc|4.32|1.00x|1.05x| |H5120 T1024|bwd|12.29|14.11 tc|12.16|1.01x|1.16x| |H5120 T1024|step|19.49|21.86 tc|19.55|1.00x|1.12x| |H5120 T4096|fwd~|11.81|13.82 qa|11.78|1.00x|1.17x| |H5120 T4096|bwd|28.06|34.24 qa|28.10|1.00x|1.22x| |H5120 T4096|step|52.16|61.63 qa|52.22|1.00x|1.18x| |H5120 T14928|fwd|46.40|46.27 qa|46.40|1.00x|1.00x| |H5120 T14928|bwd|80.64|84.90 qa|80.75|1.00x|1.05x| |H5120 T14928|step|173.65|178.05 qa|173.50|1.00x|1.03x| |H5120 T16384|fwd|50.49|50.14 qa|50.62|1.00x|0.99x| |H5120 T16384|bwd|86.91|91.42 qa|86.62|1.00x|1.06x| |H5120 T16384|step|187.90|192.85 qa|187.89|1.00x|1.03x| |H5120 T32768|fwd|99.42|98.11 qa|99.36|1.00x|0.99x| |H5120 T32768|bwd|161.92|165.09 qa|162.00|1.00x|1.02x| |H5120 T32768|step|358.24|360.13 qa|358.49|1.00x|1.00x| |H5120 T65536|fwd|197.81|196.32 qa|197.66|1.00x|0.99x| |H5120 T65536|bwd|310.30|379.90 tc|310.11|1.00x|1.23x| |H5120 T65536|step|700.27|780.09 tc|699.26|1.00x|1.12x| |H6144 T1|fwd~|2.69|2.24 qa|2.69|1.00x|0.83x| |H6144 T1|bwd~|6.24|3.10 tc|3.81|1.64x|0.82x| |H6144 T1|step~|10.88|7.23 tc|8.64|1.26x|0.84x| |H6144 T4|fwd~|2.53|2.08 qa|2.53|1.00x|0.82x| |H6144 T4|bwd~|6.17|4.70 tcd|3.94|1.57x|1.20x| |H6144 T4|step~|10.69|8.83 tc|8.83|1.21x|1.00x| |H6144 T16|fwd|2.66|2.14 lg|2.66|1.00x|0.81x| |H6144 T16|bwd~|6.05|4.96 tc|3.94|1.54x|1.26x| |H6144 T16|step~|11.23|9.18 tcd|9.09|1.24x|1.01x| |H6144 T64|fwd~|2.62|2.18 lg|2.62|1.00x|0.83x| |H6144 T64|bwd|6.37|4.86 tc|5.06|1.26x|0.96x| |H6144 T64|step|10.37|9.12 tcd|9.41|1.10x|0.97x| |H6144 T256|fwd|2.91|2.78 lg|2.91|1.00x|0.96x| |H6144 T256|bwd|7.71|8.61 tc|6.82|1.13x|1.26x| |H6144 T256|step|12.16|13.28 tc|11.68|1.04x|1.14x| |H6144 T1024|fwd|4.77|4.99 qa|4.77|1.00x|1.05x| |H6144 T1024|bwd|15.01|16.61 tc|14.08|1.07x|1.18x| |H6144 T1024|step|23.97|24.80 tc|23.23|1.03x|1.07x| |H6144 T4096|fwd|15.52|16.35 qa|15.49|1.00x|1.06x| |H6144 T4096|bwd|32.54|38.11 qa|32.74|0.99x|1.16x| |H6144 T4096|step|63.81|71.46 qa|62.81|1.02x|1.14x| |H6144 T14928|fwd|52.48|55.41 q|52.41|1.00x|1.06x| |H6144 T14928|bwd|95.26|97.41 qa|93.06|1.02x|1.05x| |H6144 T14928|step|201.31|208.45 qa|199.81|1.01x|1.04x| |H6144 T16384|fwd|57.73|59.42 qa|57.82|1.00x|1.03x| |H6144 T16384|bwd|102.40|104.83 qa|100.51|1.02x|1.04x| |H6144 T16384|step|217.76|224.27 qa|215.93|1.01x|1.04x| |H6144 T32768|fwd|114.53|115.97 qa|114.17|1.00x|1.02x| |H6144 T32768|bwd|192.22|191.93 qa|190.40|1.01x|1.01x| |H6144 T32768|step|420.73|424.38 qa|418.99|1.00x|1.01x| |H6144 T65536|fwd|231.74|232.51 q|231.97|1.00x|1.00x| |H6144 T65536|bwd|368.00|396.70 tc|365.89|1.01x|1.08x| |H6144 T65536|step|824.86|881.77 tc|823.34|1.00x|1.07x| |H6144 T1 res|fwd~|3.04|2.69 lg|3.07|0.99x|0.88x| |H6144 T1 res|bwd~|7.07|3.10 tc|4.06|1.74x|0.76x| |H6144 T1 res|step~|11.84|8.13 tc|9.54|1.24x|0.85x| |H6144 T4 res|fwd~|2.85|2.53 lg|2.82|1.01x|0.90x| |H6144 T4 res|bwd~|6.66|4.93 tc|3.90|1.70x|1.26x| |H6144 T4 res|step~|11.10|9.44 tc|8.80|1.26x|1.07x| |H6144 T16 res|fwd~|2.98|2.62 lg|2.91|1.02x|0.90x| |H6144 T16 res|bwd~|7.01|6.18 tc|4.16|1.68x|1.48x| |H6144 T16 res|step~|12.22|11.42 tc|9.79|1.25x|1.17x| |H6144 T64 res|fwd|3.20|2.91 lg|3.20|1.00x|0.91x| |H6144 T64 res|bwd|7.04|5.95 tc|5.34|1.32x|1.11x| |H6144 T64 res|step~|13.25|12.13 tc|11.33|1.17x|1.07x| |H6144 T256 res|fwd|4.51|4.45 lg|4.51|1.00x|0.99x| |H6144 T256 res|bwd~|9.44|10.08 tc|7.14|1.32x|1.41x| |H6144 T256 res|step~|17.70|19.14 tc|15.68|1.13x|1.22x| |H6144 T1024 res|fwd|10.43|10.27 lg|10.43|1.00x|0.98x| |H6144 T1024 res|bwd|20.16|18.40 tc|16.16|1.25x|1.14x| |H6144 T1024 res|step|38.34|38.66 tc|34.40|1.11x|1.12x| |H6144 T4096 res|fwd|33.63|32.80 tc|33.18|1.01x|0.99x| |H6144 T4096 res|bwd|48.54|47.46 qa|38.98|1.25x|1.22x| |H6144 T4096 res|step|114.05|123.92 tc|102.53|1.11x|1.21x| |H6144 T14928 res|fwd|109.95|108.86 lg|110.18|1.00x|0.99x| |H6144 T14928 res|bwd|143.49|129.25 qa|122.62|1.17x|1.05x| |H6144 T14928 res|step|361.89|386.14 tc|340.09|1.06x|1.14x| |H6144 T16384 res|fwd|120.34|118.81 lg|120.38|1.00x|0.99x| |H6144 T16384 res|bwd|156.06|136.99 qa|132.99|1.17x|1.03x| |H6144 T16384 res|step|395.13|394.01 tc|370.78|1.07x|1.06x| |H6144 T32768 res|fwd|237.01|234.37 lg|237.09|1.00x|0.99x| |H6144 T32768 res|bwd|298.21|253.73 qa|259.61|1.15x|0.98x| |H6144 T32768 res|step|769.79|745.50 tc|730.54|1.05x|1.02x| |H6144 T65536 res|fwd|469.07|464.28 lg|468.77|1.00x|0.99x| |H6144 T65536 res|bwd|579.10|506.57 tc|511.20|1.13x|0.99x| |H6144 T65536 res|step|1521.75|1447.98 tc|1446.82|1.05x|1.00x| |H2048 T1 w32|fwd~|1.92|1.86 lg|1.86|1.03x|1.00x| |H2048 T1 w32|bwd~|5.79|2.02 tc|3.84|1.51x|0.53x| |H2048 T1 w32|step~|8.64|5.26 tc|6.98|1.24x|0.75x| |H2048 T4 w32|fwd~|1.82|1.86 lg|1.86|0.98x|1.00x| |H2048 T4 w32|bwd~|6.14|3.46 tc|3.87|1.59x|0.89x| |H2048 T4 w32|step~|8.86|6.82 tc|6.88|1.29x|0.99x| |H2048 T16 w32|fwd|1.89|1.82 lg|1.89|1.00x|0.97x| |H2048 T16 w32|bwd~|6.02|4.45 tc|3.87|1.55x|1.15x| |H2048 T16 w32|step~|9.47|9.41 tc|7.58|1.25x|1.24x| |H2048 T64 w32|fwd|1.92|1.86 lg|1.92|1.00x|0.97x| |H2048 T64 w32|bwd|6.21|4.58 tc|4.00|1.55x|1.14x| |H2048 T64 w32|step|9.54|8.22 tc|8.00|1.19x|1.03x| |H4096 T1 w32|fwd~|1.98|2.24 q|1.95|1.02x|1.15x| |H4096 T1 w32|bwd~|5.76|2.62 tc|3.84|1.50x|0.68x| |H4096 T1 w32|step~|9.28|6.75 tcd|7.71|1.20x|0.88x| |H4096 T4 w32|fwd~|2.02|1.95 lg|1.98|1.02x|0.98x| |H4096 T4 w32|bwd~|5.76|4.35 tcd|3.90|1.48x|1.11x| |H4096 T4 w32|step~|8.93|8.10 tcd|7.90|1.13x|1.02x| |H4096 T16 w32|fwd|2.02|2.02 lg|2.02|1.00x|1.00x| |H4096 T16 w32|bwd~|5.92|4.51 tcd|3.90|1.52x|1.16x| |H4096 T16 w32|step~|9.31|8.35 tcd|7.74|1.20x|1.08x| |H4096 T64 w32|fwd|2.08|2.11 lg|2.05|1.02x|1.03x| |H4096 T64 w32|bwd~|5.98|4.70 tc|4.38|1.36x|1.07x| |H4096 T64 w32|step~|9.74|8.64 tc|8.56|1.14x|1.01x| |H5120 T256 w32|fwd|2.72|2.78 qa|2.72|1.00x|1.02x| |H5120 T256 w32|bwd~|7.68|8.80 tc|7.71|1.00x|1.14x| |H5120 T256 w32|step~|12.29|14.53 tc|12.32|1.00x|1.18x| |H5120 T1024 w32|fwd~|4.58|4.99 tc|4.61|0.99x|1.08x| |H5120 T1024 w32|bwd|12.93|14.46 tc|12.77|1.01x|1.13x| |H5120 T1024 w32|step~|20.10|22.50 tc|20.26|0.99x|1.11x| |H5120 T4096 w32|fwd|12.35|15.52 qa|12.26|1.01x|1.27x| |H5120 T4096 w32|bwd|28.57|32.35 qa|28.45|1.00x|1.14x| |H5120 T4096 w32|step|53.18|61.47 qa|53.57|0.99x|1.15x| |H5120 T14928 w32|fwd|45.86|47.49 qa|46.30|0.99x|1.03x| |H5120 T14928 w32|bwd|81.10|82.94 qa|81.09|1.00x|1.02x| |H5120 T14928 w32|step|173.73|178.85 qa|174.22|1.00x|1.03x| |H5120 T16384 w32|fwd|50.05|51.45 qa|50.30|0.99x|1.02x| |H5120 T16384 w32|bwd|86.88|89.41 qa|86.94|1.00x|1.03x| |H5120 T16384 w32|step|187.74|192.96 qa|188.45|1.00x|1.02x| |H5120 T32768 w32|fwd|101.44|101.22 qa|98.88|1.03x|1.02x| |H5120 T32768 w32|bwd|162.94|162.02 qa|162.59|1.00x|1.00x| |H5120 T32768 w32|step|362.41|360.38 qa|361.82|1.00x|1.00x| |H5120 T65536 w32|fwd|198.14|195.42 qa|198.88|1.00x|0.98x| |H5120 T65536 w32|bwd|313.18|392.33 tc|313.28|1.00x|1.25x| |H5120 T65536 w32|step|707.80|784.97 tc|707.26|1.00x|1.11x| |H6144 T1 w32|fwd~|2.62|2.27 qa|2.66|0.99x|0.86x| |H6144 T1 w32|bwd~|6.34|3.55 tcd|3.74|1.69x|0.95x| |H6144 T1 w32|step~|10.91|7.94 tcd|8.35|1.31x|0.95x| |H6144 T4 w32|fwd~|2.43|2.11 qa|2.40|1.01x|0.88x| |H6144 T4 w32|bwd~|6.21|4.86 tcd|3.75|1.66x|1.30x| |H6144 T4 w32|step~|10.53|9.22 tcd|8.64|1.22x|1.07x| |H6144 T16 w32|fwd|2.43|2.18 qa|2.43|1.00x|0.89x| |H6144 T16 w32|bwd~|6.21|5.21 tc|3.81|1.63x|1.37x| |H6144 T16 w32|step~|10.88|9.60 tcd|8.42|1.29x|1.14x| |H6144 T64 w32|fwd|2.53|2.30 lg|2.53|1.00x|0.91x| |H6144 T64 w32|bwd~|6.43|5.34 tc|5.06|1.27x|1.06x| |H6144 T64 w32|step~|10.82|9.98 tc|10.11|1.07x|0.99x| |H6144 T256 w32|fwd|2.98|2.98 qa|2.94|1.01x|1.01x| |H6144 T256 w32|bwd|7.78|8.42 tc|6.69|1.16x|1.26x| |H6144 T256 w32|step|12.35|13.66 tc|11.65|1.06x|1.17x| |H6144 T1024 w32|fwd~|5.78|5.49 tcd|5.82|0.99x|0.94x| |H6144 T1024 w32|bwd|14.82|17.09 tc|13.87|1.07x|1.23x| |H6144 T1024 w32|step|25.28|26.82 tc|24.67|1.02x|1.09x| |H6144 T4096 w32|fwd|16.29|17.82 qa|16.26|1.00x|1.10x| |H6144 T4096 w32|bwd|32.96|36.19 qa|33.18|0.99x|1.09x| |H6144 T4096 w32|step|62.40|71.26 qa|64.58|0.97x|1.10x| |H6144 T14928 w32|fwd|56.99|56.38 tcd|55.58|1.03x|1.01x| |H6144 T14928 w32|bwd|95.26|95.36 qa|93.09|1.02x|1.02x| |H6144 T14928 w32|step|206.11|206.89 qa|204.25|1.01x|1.01x| |H6144 T16384 w32|fwd|62.94|62.64 qa|60.58|1.04x|1.03x| |H6144 T16384 w32|bwd|102.85|103.07 qa|100.06|1.03x|1.03x| |H6144 T16384 w32|step|223.04|223.87 qa|220.41|1.01x|1.02x| |H6144 T32768 w32|fwd|119.87|120.29 qa|117.89|1.02x|1.02x| |H6144 T32768 w32|bwd|192.19|189.63 qa|189.68|1.01x|1.00x| |H6144 T32768 w32|step|426.88|426.14 qa|424.51|1.01x|1.00x| |H6144 T65536 w32|fwd|233.98|233.89 qa|233.76|1.00x|1.00x| |H6144 T65536 w32|bwd|369.42|411.77 tc|365.28|1.01x|1.13x| |H6144 T65536 w32|step|834.08|900.49 tc|829.75|1.01x|1.09x| |H6144 T1 res w32|fwd~|3.07|2.81 lg|3.01|1.02x|0.94x| |H6144 T1 res w32|bwd~|6.69|3.36 tc|3.84|1.74x|0.88x| |H6144 T1 res w32|step~|12.37|8.69 tc|9.54|1.30x|0.91x| |H6144 T4 res w32|fwd~|2.82|2.56 lg|2.85|0.99x|0.90x| |H6144 T4 res w32|bwd~|6.75|5.89 tc|3.84|1.76x|1.53x| |H6144 T4 res w32|step~|11.47|10.82 tc|9.22|1.24x|1.17x| |H6144 T16 res w32|fwd~|2.91|2.72 lg|2.91|1.00x|0.93x| |H6144 T16 res w32|bwd~|6.66|5.09 tc|3.94|1.69x|1.29x| |H6144 T16 res w32|step~|11.10|9.57 tc|9.12|1.22x|1.05x| |H6144 T64 res w32|fwd|3.20|2.98 lg|3.20|1.00x|0.93x| |H6144 T64 res w32|bwd|7.10|5.95 tc|5.18|1.37x|1.15x| |H6144 T64 res w32|step~|11.87|11.14 tc|10.53|1.13x|1.06x| |H6144 T256 res w32|fwd|4.64|4.48 lg|4.64|1.00x|0.97x| |H6144 T256 res w32|bwd~|9.34|10.24 tc|7.14|1.31x|1.43x| |H6144 T256 res w32|step~|17.73|19.46 tc|15.62|1.14x|1.25x| |H6144 T1024 res w32|fwd|11.23|10.62 lg|11.17|1.01x|0.95x| |H6144 T1024 res w32|bwd|20.38|21.26 qa|16.35|1.25x|1.30x| |H6144 T1024 res w32|step|39.87|41.50 lg|36.19|1.10x|1.15x| |H6144 T4096 res w32|fwd|32.70|33.09 lg|32.72|1.00x|1.01x| |H6144 T4096 res w32|bwd|48.74|47.39 qa|38.94|1.25x|1.22x| |H6144 T4096 res w32|step|111.52|129.82 tc|102.11|1.09x|1.27x| |H6144 T14928 res w32|fwd|109.60|109.60 tc|109.22|1.00x|1.00x| |H6144 T14928 res w32|bwd|141.09|128.40 qa|122.14|1.16x|1.05x| |H6144 T14928 res w32|step|357.98|403.77 qa|338.01|1.06x|1.19x| |H6144 T16384 res w32|fwd|119.94|119.84 lg|120.03|1.00x|1.00x| |H6144 T16384 res w32|bwd|153.79|139.39 qa|132.83|1.16x|1.05x| |H6144 T16384 res w32|step|391.55|429.42 tc|370.43|1.06x|1.16x| |H6144 T32768 res w32|fwd|235.33|235.81 lg|236.09|1.00x|1.00x| |H6144 T32768 res w32|bwd|292.64|258.85 qa|259.58|1.13x|1.00x| |H6144 T32768 res w32|step|761.85|813.75 tc|729.21|1.04x|1.12x| |H6144 T65536 res w32|fwd|466.24|467.02 lg|466.43|1.00x|1.00x| |H6144 T65536 res w32|bwd|569.28|634.78 tc|510.88|1.11x|1.24x| |H6144 T65536 res w32|step|1505.26|1585.43 tc|1442.68|1.04x|1.10x| |[T,24,256] T1024|fwd~|6.66|6.27 tcd|6.62|1.00x|0.95x| |[T,24,256] T1024|bwd|15.81|24.45 tc|15.46|1.02x|1.58x| |[T,24,256] T1024|step~|24.54|34.37 tc|25.04|0.98x|1.37x| |[T,24,256] T4096|fwd|18.11|17.82 tcd|18.08|1.00x|0.99x| |[T,24,256] T4096|bwd|35.55|43.71 tcd|35.33|1.01x|1.24x| |[T,24,256] T4096|step|66.85|72.22 tcd|66.05|1.01x|1.09x| |[T,24,256] T16384|fwd|62.00|62.24 tcd|62.10|1.00x|1.00x| |[T,24,256] T16384|bwd|105.82|113.31 tc|114.85|0.92x|0.99x| |[T,24,256] T16384|step|227.74|241.30 tc|236.86|0.96x|1.02x| |[T,24,256] T65536|fwd|236.00|238.14 tcd|236.06|1.00x|1.01x| |[T,24,256] T65536|bwd!|384.89|386.56 tc|427.77|0.90x|0.90x| |[T,24,256] T65536|step!|858.63|876.80 tc|898.87|0.96x|0.98x| |[T,4,256] T1024|fwd|2.75|2.69 tcd|2.78|0.99x|0.97x| |[T,4,256] T1024|bwd~|7.87|8.48 tc|7.71|1.02x|1.10x| |[T,4,256] T1024|step~|12.99|12.90 tc|12.22|1.06x|1.05x| |[T,4,256] T4096|fwd|5.12|4.74 tcd|5.22|0.98x|0.91x| |[T,4,256] T4096|bwd~|12.83|13.98 tc|12.90|1.00x|1.08x| |[T,4,256] T4096|step|18.91|20.42 tc|19.30|0.98x|1.06x| |[T,4,256] T16384|fwd|12.64|12.26 tcd|12.61|1.00x|0.97x| |[T,4,256] T16384|bwd|26.05|34.91 tcd|26.40|0.99x|1.32x| |[T,4,256] T16384|step|45.28|55.52 tcd|44.83|1.01x|1.24x| |[T,4,256] T65536|fwd|42.43|41.85 tc|42.43|1.00x|0.99x| |[T,4,256] T65536|bwd|74.88|82.05 tc|79.49|0.94x|1.03x| |[T,4,256] T65536|step|158.08|164.86 tc|162.43|0.97x|1.01x| **GB300 (sm_103a)** GB300, 152 SMs, sm_103a, compute capability 10.3, driver 580.159.03, CUDA 13.4 (same nvcc as B200), torch 2.14.1+cu130. SM clock 2070 MHz (100 % of samples at max), memory clock 3996 MHz, 4 GPUs of one node. Rows: 78 shapes + 20 small-T shapes + 9 window shapes, x 3 ops = 321 rows. The small-T shapes are T1, T4, T16 and T64 of H5120, H6144, H6144 w32, H6144 res and H6144 res w32. The window shapes are H5120 T321/T512/T896, plus T449/T768/T1152 of H6144 and H6144 w32. New, det and SOTA meet the budget on every row. - `~`: 86 rows - no `!` or `*` rows | op | geomean vs det [min, max] | rows < 1 | geomean vs SOTA [min, max] | rows < 1 | | --- | --- | --- | --- | --- | | fwd (78) | 1.001x [0.966, 1.045] | 25 | 1.017x [0.935, 1.329] | 34 | | bwd (78) | 0.991x [0.790, 1.163] | 41 | 1.146x [0.847, 1.583] | 19 | | 2xfwd+bwd (78) | 0.998x [0.867, 1.051] | 36 | 1.138x [0.944, 1.545] | 5 | | fwd (small-T 20) | 1.000x [0.979, 1.014] | 6 | 0.888x [0.739, 0.969] | 20 | | bwd (small-T 20) | 1.173x [0.916, 1.457] | 5 | 1.055x [0.736, 1.478] | 8 | | 2xfwd+bwd (small-T 20) | 1.073x [0.931, 1.195] | 5 | 1.195x [1.004, 1.702] | 0 | | fwd (window 9) | 0.999x [0.980, 1.020] | 4 | 1.026x [0.900, 1.107] | 2 | | bwd (window 9) | 0.971x [0.962, 0.996] | 9 | 1.219x [1.078, 1.342] | 0 | | 2xfwd+bwd (window 9) | 0.998x [0.983, 1.009] | 4 | 1.242x [1.131, 1.345] | 0 | | workload / shape / dtype / mode | operation | deterministic Cake latency (us) | non-Cake SOTA latency (us) | new non-deterministic Cake latency (us) | speedup vs deterministic Cake | speedup vs non-Cake SOTA | |---|---|---|---|---|---|---| |H512 T256|fwd|2.14|2.05 tcd|2.14|1.00x|0.96x| |H512 T256|bwd|5.22|7.04 tcd|5.44|0.96x|1.29x| |H512 T256|step|9.09|10.46 tcd|8.96|1.01x|1.17x| |H512 T1024|fwd|2.40|2.34 lg|2.43|0.99x|0.96x| |H512 T1024|bwd~|5.89|8.03 tc|5.79|1.02x|1.39x| |H512 T1024|step|9.63|13.41 tc|9.79|0.98x|1.37x| |H512 T4096|fwd|3.52|3.39 tcd|3.58|0.98x|0.95x| |H512 T4096|bwd~|10.43|12.06 tcd|10.37|1.01x|1.16x| |H512 T4096|step~|15.26|17.06 tcd|15.30|1.00x|1.12x| |H512 T14928|fwd|6.91|6.94 q|6.88|1.00x|1.01x| |H512 T14928|bwd|15.27|23.84 qa|15.23|1.00x|1.57x| |H512 T14928|step|25.76|35.14 qa|25.44|1.01x|1.38x| |H512 T16384|fwd|7.42|7.26 tcd|7.33|1.01x|0.99x| |H512 T16384|bwd|15.46|23.17 tc|15.39|1.00x|1.51x| |H512 T16384|step|26.94|35.39 tc|26.91|1.00x|1.32x| |H512 T32768|fwd|12.38|11.94 tcd|12.29|1.01x|0.97x| |H512 T32768|bwd|23.01|33.50 qa|23.20|0.99x|1.44x| |H512 T32768|step|43.52|54.21 tc|43.62|1.00x|1.24x| |H512 T65536|fwd|22.21|21.98 tcd|21.98|1.01x|1.00x| |H512 T65536|bwd|40.06|50.02 qa|40.32|0.99x|1.24x| |H512 T65536|step~|80.83|97.26 tc|80.61|1.00x|1.21x| |H1536 T256|fwd|1.98|1.92 lg|1.98|1.00x|0.97x| |H1536 T256|bwd~|5.76|8.70 tcd|5.86|0.98x|1.49x| |H1536 T256|step~|9.44|13.22 tcd|9.54|0.99x|1.39x| |H1536 T1024|fwd~|2.53|2.66 q|2.56|0.99x|1.04x| |H1536 T1024|bwd~|7.14|10.46 tcd|7.33|0.97x|1.43x| |H1536 T1024|step~|11.62|16.19 tcd|11.87|0.98x|1.36x| |H1536 T4096|fwd~|4.48|5.22 qa|4.64|0.97x|1.12x| |H1536 T4096|bwd|12.93|19.97 tcd|12.86|1.00x|1.55x| |H1536 T4096|step|19.78|30.40 tcd|19.68|1.00x|1.54x| |H1536 T14928|fwd|13.15|14.37 qa|12.93|1.02x|1.11x| |H1536 T14928|bwd|28.96|39.78 qa|28.93|1.00x|1.38x| |H1536 T14928|step|51.23|63.55 qa|51.33|1.00x|1.24x| |H1536 T16384|fwd|14.05|15.39 q|14.11|1.00x|1.09x| |H1536 T16384|bwd|30.43|41.86 qa|30.40|1.00x|1.38x| |H1536 T16384|step|54.66|68.70 qa|54.78|1.00x|1.25x| |H1536 T32768|fwd|28.00|29.79 qa|27.94|1.00x|1.07x| |H1536 T32768|bwd|53.31|64.77 qa|53.54|1.00x|1.21x| |H1536 T32768|step|110.50|123.84 qa|107.65|1.03x|1.15x| |H1536 T65536|fwd|55.94|58.34 qa|56.10|1.00x|1.04x| |H1536 T65536|bwd|101.47|108.74 qa|128.45|0.79x|0.85x| |H1536 T65536|step|218.75|225.15 qa|238.53|0.92x|0.94x| |H2048 T256|fwd|2.08|1.98 lg|2.05|1.02x|0.97x| |H2048 T256|bwd~|6.34|7.94 tcd|6.18|1.03x|1.28x| |H2048 T256|step~|10.08|13.38 tcd|10.14|0.99x|1.32x| |H2048 T1024|fwd|2.69|2.82 lg|2.72|0.99x|1.04x| |H2048 T1024|bwd~|8.10|10.30 tcd|8.22|0.98x|1.25x| |H2048 T1024|step|12.64|15.74 tcd|12.51|1.01x|1.26x| |H2048 T4096|fwd~|5.60|6.05 qa|5.66|0.99x|1.07x| |H2048 T4096|bwd|17.15|18.85 tc|17.12|1.00x|1.10x| |H2048 T4096|step~|26.59|29.06 tc|26.88|0.99x|1.08x| |H2048 T14928|fwd|17.25|17.86 q|17.18|1.00x|1.04x| |H2048 T14928|bwd|36.74|47.71 tc|36.70|1.00x|1.30x| |H2048 T14928|step|70.98|83.78 qa|71.01|1.00x|1.18x| |H2048 T16384|fwd~|18.72|19.36 q|18.72|1.00x|1.03x| |H2048 T16384|bwd|39.81|51.33 tc|40.00|1.00x|1.28x| |H2048 T16384|step|77.79|89.60 tc|77.79|1.00x|1.15x| |H2048 T32768|fwd|37.70|38.18 q|37.09|1.02x|1.03x| |H2048 T32768|bwd|68.99|82.85 tc|68.67|1.00x|1.21x| |H2048 T32768|step|144.77|162.88 qa|144.26|1.00x|1.13x| |H2048 T65536|fwd|74.78|75.07 q|74.75|1.00x|1.00x| |H2048 T65536|bwd|128.50|143.20 qa|144.88|0.89x|0.99x| |H2048 T65536|step|278.67|296.32 qa|291.98|0.95x|1.01x| |H4096 T256|fwd|2.34|2.30 lg|2.34|1.00x|0.99x| |H4096 T256|bwd~|6.85|8.37 tcd|6.75|1.01x|1.24x| |H4096 T256|step~|10.37|12.91 tcd|10.30|1.01x|1.25x| |H4096 T1024|fwd~|3.62|3.97 tcd|3.58|1.01x|1.11x| |H4096 T1024|bwd|11.36|13.79 tcd|11.23|1.01x|1.23x| |H4096 T1024|step|16.83|20.32 tcd|16.96|0.99x|1.20x| |H4096 T4096|fwd|9.47|10.27 qa|9.71|0.98x|1.06x| |H4096 T4096|bwd|23.55|28.45 qa|23.65|1.00x|1.20x| |H4096 T4096|step|42.37|47.26 qa|42.46|1.00x|1.11x| |H4096 T14928|fwd|34.66|34.75 qa|34.43|1.01x|1.01x| |H4096 T14928|bwd|68.29|67.01 qa|68.26|1.00x|0.98x| |H4096 T14928|step|138.21|138.30 qa|137.60|1.00x|1.01x| |H4096 T16384|fwd|38.08|39.42 q|37.92|1.00x|1.04x| |H4096 T16384|bwd|73.28|73.06 qa|72.96|1.00x|1.00x| |H4096 T16384|step|149.79|153.44 qa|149.18|1.00x|1.03x| |H4096 T32768|fwd|74.91|76.64 q|74.94|1.00x|1.02x| |H4096 T32768|bwd|132.54|130.75 qa|133.02|1.00x|0.98x| |H4096 T32768|step|281.60|286.05 qa|282.02|1.00x|1.01x| |H4096 T65536|fwd|151.97|151.74 tcd|150.10|1.01x|1.01x| |H4096 T65536|bwd|249.76|244.40 qa|257.86|0.97x|0.95x| |H4096 T65536|step|551.33|550.51 qa|558.16|0.99x|0.99x| |H5120 T1|fwd~|2.34|2.11 qa|2.34|1.00x|0.90x| |H5120 T1|bwd~|5.73|3.55 tcd|4.48|1.28x|0.79x| |H5120 T1|step~|9.57|8.93 tcd|8.35|1.15x|1.07x| |H5120 T4|fwd~|2.05|2.02 lg|2.08|0.98x|0.97x| |H5120 T4|bwd~|5.79|5.18 tcd|4.51|1.28x|1.15x| |H5120 T4|step|8.96|9.41 tcd|8.00|1.12x|1.18x| |H5120 T16|fwd~|2.14|2.02 lg|2.14|1.00x|0.94x| |H5120 T16|bwd~|5.60|5.54 tcd|4.86|1.15x|1.14x| |H5120 T16|step~|9.60|11.52 tcd|8.93|1.08x|1.29x| |H5120 T64|fwd|2.18|2.08 lg|2.18|1.00x|0.96x| |H5120 T64|bwd|5.86|6.11 tcd|5.86|1.00x|1.04x| |H5120 T64|step~|10.05|11.84 tcd|9.86|1.02x|1.20x| |H5120 T256|fwd|2.59|2.62 lg|2.59|1.00x|1.01x| |H5120 T256|bwd|7.17|9.47 tcd|7.42|0.97x|1.28x| |H5120 T256|step|10.85|14.65 tcd|10.98|0.99x|1.34x| |H5120 T321|fwd|2.85|2.94 lg|2.85|1.00x|1.03x| |H5120 T321|bwd|8.29|11.17 tcd|8.32|1.00x|1.34x| |H5120 T321|step|13.31|17.34 tcd|13.47|0.99x|1.29x| |H5120 T512|fwd|3.20|3.46 qa|3.26|0.98x|1.06x| |H5120 T512|bwd|9.52|12.58 tcd|9.86|0.97x|1.28x| |H5120 T512|step|15.58|19.62 tcd|15.55|1.00x|1.26x| |H5120 T896|fwd|3.78|4.16 tcd|3.81|0.99x|1.09x| |H5120 T896|bwd|11.30|14.78 tc|11.74|0.96x|1.26x| |H5120 T896|step~|17.95|23.94 qa|17.79|1.01x|1.35x| |H5120 T1024|fwd|4.19|4.32 qa|4.16|1.01x|1.04x| |H5120 T1024|bwd|12.00|16.26 tc|12.67|0.95x|1.28x| |H5120 T1024|step|18.94|24.61 qa|18.91|1.00x|1.30x| |H5120 T4096|fwd|11.46|13.44 qa|11.46|1.00x|1.17x| |H5120 T4096|bwd|26.85|33.31 qa|26.85|1.00x|1.24x| |H5120 T4096|step|49.54|58.43 qa|49.25|1.01x|1.19x| |H5120 T14928|fwd|44.54|44.13 qa|44.32|1.01x|1.00x| |H5120 T14928|bwd|79.14|83.41 qa|79.17|1.00x|1.05x| |H5120 T14928|step|169.65|173.44 qa|161.47|1.05x|1.07x| |H5120 T16384|fwd|48.83|48.42 qa|48.86|1.00x|0.99x| |H5120 T16384|bwd|86.38|89.38 qa|86.34|1.00x|1.04x| |H5120 T16384|step|185.79|188.29 qa|177.22|1.05x|1.06x| |H5120 T32768|fwd|95.87|94.82 qa|95.84|1.00x|0.99x| |H5120 T32768|bwd|163.09|199.58 tc|163.42|1.00x|1.22x| |H5120 T32768|step|355.33|396.64 q|346.05|1.03x|1.15x| |H5120 T65536|fwd|191.30|188.48 qa|191.30|1.00x|0.99x| |H5120 T65536|bwd|314.30|362.08 tc|363.10|0.87x|1.00x| |H5120 T65536|step|692.64|750.50 tc|743.30|0.93x|1.01x| |H6144 T1|fwd~|2.94|2.18 lg|2.94|1.00x|0.74x| |H6144 T1|bwd~|6.18|3.49 tc|4.45|1.39x|0.78x| |H6144 T1|step~|10.94|9.60 tcd|9.22|1.19x|1.04x| |H6144 T4|fwd~|2.43|2.02 qa|2.43|1.00x|0.83x| |H6144 T4|bwd~|5.73|5.28 tcd|5.89|0.97x|0.90x| |H6144 T4|step~|10.53|10.85 tcd|10.40|1.01x|1.04x| |H6144 T16|fwd~|2.46|2.05 lg|2.48|0.99x|0.83x| |H6144 T16|bwd|6.02|5.47 tcd|6.02|1.00x|0.91x| |H6144 T16|step|9.98|10.85 tcd|9.98|1.00x|1.09x| |H6144 T64|fwd~|2.66|2.14 lg|2.62|1.01x|0.82x| |H6144 T64|bwd~|6.14|6.02 tcd|6.21|0.99x|0.97x| |H6144 T64|step~|10.05|11.49 tcd|10.08|1.00x|1.14x| |H6144 T256|fwd|2.85|2.69 lg|2.85|1.00x|0.94x| |H6144 T256|bwd~|7.49|9.73 tcd|7.68|0.98x|1.27x| |H6144 T256|step~|11.87|15.33 tcd|11.97|0.99x|1.28x| |H6144 T449|fwd|3.26|3.17 lg|3.20|1.02x|0.99x| |H6144 T449|bwd~|9.60|12.93 tcd|9.98|0.96x|1.30x| |H6144 T449|step~|15.30|20.19 tc|15.26|1.00x|1.32x| |H6144 T768|fwd|3.90|4.16 qa|3.94|0.99x|1.06x| |H6144 T768|bwd~|12.75|14.53 tc|13.18|0.97x|1.10x| |H6144 T768|step~|20.61|25.31 qa|20.51|1.00x|1.23x| |H6144 T1024|fwd|4.64|4.77 qa|4.64|1.00x|1.03x| |H6144 T1024|bwd|14.37|19.11 qa|14.78|0.97x|1.29x| |H6144 T1024|step|23.14|27.55 qa|23.14|1.00x|1.19x| |H6144 T1152|fwd|5.79|5.18 qa|5.76|1.01x|0.90x| |H6144 T1152|bwd|15.20|19.74 qa|15.71|0.97x|1.26x| |H6144 T1152|step|25.15|29.18 qa|25.06|1.00x|1.16x| |H6144 T4096|fwd|14.85|15.55 qa|14.85|1.00x|1.05x| |H6144 T4096|bwd|31.46|36.32 qa|32.13|0.98x|1.13x| |H6144 T4096|step|60.64|66.43 qa|60.16|1.01x|1.10x| |H6144 T14928|fwd|51.33|53.79 q|51.14|1.00x|1.05x| |H6144 T14928|bwd|93.38|94.18 qa|93.44|1.00x|1.01x| |H6144 T14928|step|196.19|201.28 qa|196.13|1.00x|1.03x| |H6144 T16384|fwd|56.27|58.27 q|56.22|1.00x|1.04x| |H6144 T16384|bwd|100.42|101.41 qa|100.35|1.00x|1.01x| |H6144 T16384|step|213.02|218.10 qa|212.70|1.00x|1.03x| |H6144 T32768|fwd|111.94|113.95 q|111.84|1.00x|1.02x| |H6144 T32768|bwd|188.98|185.06 qa|188.83|1.00x|0.98x| |H6144 T32768|step|412.67|411.79 qa|413.06|1.00x|1.00x| |H6144 T65536|fwd|227.33|226.75 qa|227.68|1.00x|1.00x| |H6144 T65536|bwd|366.59|389.97 tc|384.80|0.95x|1.01x| |H6144 T65536|step|814.27|858.24 tc|833.53|0.98x|1.03x| |H6144 T1 res|fwd~|2.91|2.66 lg|2.88|1.01x|0.92x| |H6144 T1 res|bwd~|6.53|4.99 tc|4.48|1.46x|1.11x| |H6144 T1 res|step~|11.36|10.94 tc|9.50|1.20x|1.15x| |H6144 T4 res|fwd~|2.66|2.50 lg|2.69|0.99x|0.93x| |H6144 T4 res|bwd~|6.14|6.43 tcd|4.61|1.33x|1.40x| |H6144 T4 res|step~|11.17|16.99 tcd|9.98|1.12x|1.70x| |H6144 T16 res|fwd|2.82|2.59 lg|2.82|1.00x|0.92x| |H6144 T16 res|bwd|6.64|7.42 tcd|5.02|1.32x|1.48x| |H6144 T16 res|step~|12.00|13.60 tc|10.59|1.13x|1.28x| |H6144 T64 res|fwd|3.04|2.85 lg|3.04|1.00x|0.94x| |H6144 T64 res|bwd|7.36|7.97 tcd|8.03|0.92x|0.99x| |H6144 T64 res|step~|12.54|17.22 lg|13.47|0.93x|1.28x| |H6144 T256 res|fwd|4.48|4.29 lg|4.48|1.00x|0.96x| |H6144 T256 res|bwd~|9.09|11.71 tc|9.57|0.95x|1.22x| |H6144 T256 res|step|16.77|21.31 lg|18.02|0.93x|1.18x| |H6144 T1024 res|fwd|10.14|10.14 lg|10.21|0.99x|0.99x| |H6144 T1024 res|bwd~|19.04|18.02 tc|16.77|1.14x|1.07x| |H6144 T1024 res|step|36.42|37.70 tc|34.64|1.05x|1.09x| |H6144 T4096 res|fwd|32.26|31.78 tcd|32.29|1.00x|0.98x| |H6144 T4096 res|bwd|47.14|46.24 qa|44.61|1.06x|1.04x| |H6144 T4096 res|step|110.24|125.86 qa|106.27|1.04x|1.18x| |H6144 T14928 res|fwd|107.17|105.54 lg|107.26|1.00x|0.98x| |H6144 T14928 res|bwd|139.33|123.90 qa|130.69|1.07x|0.95x| |H6144 T14928 res|step|351.84|377.06 tc|342.59|1.03x|1.10x| |H6144 T16384 res|fwd|117.28|115.14 lg|117.06|1.00x|0.98x| |H6144 T16384 res|bwd|150.27|135.34 qa|139.01|1.08x|0.97x| |H6144 T16384 res|step|382.91|386.02 tc|370.66|1.03x|1.04x| |H6144 T32768 res|fwd|230.56|226.50 lg|230.70|1.00x|0.98x| |H6144 T32768 res|bwd|286.56|249.34 qa|256.61|1.12x|0.97x| |H6144 T32768 res|step|744.96|722.99 tc|715.28|1.04x|1.01x| |H6144 T65536 res|fwd|456.96|447.33 lg|456.77|1.00x|0.98x| |H6144 T65536 res|bwd|557.44|488.35 tc|502.03|1.11x|0.97x| |H6144 T65536 res|step|1469.28|1398.38 tc|1413.23|1.04x|0.99x| |H5120 T256 w32|fwd|2.56|2.69 qa|2.56|1.00x|1.05x| |H5120 T256 w32|bwd~|7.20|10.05 tcd|7.46|0.97x|1.35x| |H5120 T256 w32|step~|11.26|15.26 tcd|11.71|0.96x|1.30x| |H5120 T1024 w32|fwd|4.32|4.51 tcd|4.32|1.00x|1.04x| |H5120 T1024 w32|bwd~|12.00|16.06 qa|12.58|0.95x|1.28x| |H5120 T1024 w32|step~|19.94|25.15 qa|19.89|1.00x|1.26x| |H5120 T4096 w32|fwd|11.46|15.26 qa|11.49|1.00x|1.33x| |H5120 T4096 w32|bwd|26.85|30.98 qa|26.88|1.00x|1.15x| |H5120 T4096 w32|step|49.60|59.66 qa|49.12|1.01x|1.21x| |H5120 T14928 w32|fwd|43.78|45.63 qa|44.03|0.99x|1.04x| |H5120 T14928 w32|bwd|79.90|81.41 qa|79.61|1.00x|1.02x| |H5120 T14928 w32|step|172.59|174.49 qa|164.70|1.05x|1.06x| |H5120 T16384 w32|fwd|48.06|49.79 qa|48.19|1.00x|1.03x| |H5120 T16384 w32|bwd|87.30|87.49 qa|87.01|1.00x|1.01x| |H5120 T16384 w32|step|188.51|188.99 qa|180.45|1.04x|1.05x| |H5120 T32768 w32|fwd|97.76|98.34 qa|94.88|1.03x|1.04x| |H5120 T32768 w32|bwd|162.85|158.48 qa|163.12|1.00x|0.97x| |H5120 T32768 w32|step|357.92|352.13 qa|349.07|1.03x|1.01x| |H5120 T65536 w32|fwd|191.84|190.37 qa|191.52|1.00x|0.99x| |H5120 T65536 w32|bwd|313.94|370.46 tc|369.71|0.85x|1.00x| |H5120 T65536 w32|step|697.18|762.46 tc|752.51|0.93x|1.01x| |H6144 T1 w32|fwd~|2.59|2.02 qa|2.56|1.01x|0.79x| |H6144 T1 w32|bwd~|6.08|3.30 tcd|4.48|1.36x|0.74x| |H6144 T1 w32|step~|10.14|9.15 tcd|9.12|1.11x|1.00x| |H6144 T4 w32|fwd~|2.30|2.02 qa|2.27|1.01x|0.89x| |H6144 T4 w32|bwd~|6.02|5.28 tcd|4.58|1.31x|1.15x| |H6144 T4 w32|step~|10.27|11.04 tcd|9.31|1.10x|1.19x| |H6144 T16 w32|fwd|2.40|2.08 qa|2.37|1.01x|0.88x| |H6144 T16 w32|bwd~|6.18|5.70 tcd|5.09|1.21x|1.12x| |H6144 T16 w32|step|10.53|11.49 tcd|9.82|1.07x|1.17x| |H6144 T64 w32|fwd~|2.43|2.24 lg|2.46|0.99x|0.91x| |H6144 T64 w32|bwd|6.34|5.73 tcd|6.46|0.98x|0.89x| |H6144 T64 w32|step|9.92|11.17 tcd|10.02|0.99x|1.12x| |H6144 T256 w32|fwd|2.88|2.94 lg|2.88|1.00x|1.02x| |H6144 T256 w32|bwd~|7.58|10.50 tcd|7.87|0.96x|1.33x| |H6144 T256 w32|step~|12.74|16.06 lg|12.58|1.01x|1.28x| |H6144 T449 w32|fwd|3.30|3.30 qa|3.30|1.00x|1.00x| |H6144 T449 w32|bwd~|9.70|12.64 lg|10.02|0.97x|1.26x| |H6144 T449 w32|step~|14.91|19.58 lg|15.17|0.98x|1.29x| |H6144 T768 w32|fwd|4.32|4.42 tcd|4.35|0.99x|1.01x| |H6144 T768 w32|bwd~|12.90|14.18 tc|13.15|0.98x|1.08x| |H6144 T768 w32|step|20.00|23.26 qa|20.06|1.00x|1.16x| |H6144 T1024 w32|fwd|4.96|5.18 tcd|4.93|1.01x|1.05x| |H6144 T1024 w32|bwd|14.56|17.22 q|15.04|0.97x|1.14x| |H6144 T1024 w32|step|23.90|28.22 qa|24.03|0.99x|1.17x| |H6144 T1152 w32|fwd|5.12|5.63 tcd|5.09|1.01x|1.11x| |H6144 T1152 w32|bwd|15.36|17.89 qa|15.84|0.97x|1.13x| |H6144 T1152 w32|step~|24.83|28.24 qa|24.96|0.99x|1.13x| |H6144 T4096 w32|fwd~|14.62|16.90 qa|14.58|1.00x|1.16x| |H6144 T4096 w32|bwd|31.90|34.85 qa|32.35|0.99x|1.08x| |H6144 T4096 w32|step|60.51|67.52 qa|60.26|1.00x|1.12x| |H6144 T14928 w32|fwd|53.86|54.40 qa|53.65|1.00x|1.01x| |H6144 T14928 w32|bwd|93.57|92.61 qa|93.12|1.00x|0.99x| |H6144 T14928 w32|step|198.69|201.15 qa|198.74|1.00x|1.01x| |H6144 T16384 w32|fwd|60.82|60.93 qa|58.18|1.05x|1.05x| |H6144 T16384 w32|bwd|100.83|100.58 qa|100.83|1.00x|1.00x| |H6144 T16384 w32|step|215.94|217.86 qa|215.84|1.00x|1.01x| |H6144 T32768 w32|fwd|116.06|116.74 qa|113.66|1.02x|1.03x| |H6144 T32768 w32|bwd|189.94|184.10 qa|189.70|1.00x|0.97x| |H6144 T32768 w32|step|414.98|412.98 qa|414.75|1.00x|1.00x| |H6144 T65536 w32|fwd|226.46|227.10 qa|225.76|1.00x|1.01x| |H6144 T65536 w32|bwd|366.08|400.26 tc|391.01|0.94x|1.02x| |H6144 T65536 w32|step|811.33|865.98 tc|838.40|0.97x|1.03x| |H6144 T1 res w32|fwd~|3.01|2.66 lg|3.07|0.98x|0.86x| |H6144 T1 res w32|bwd~|6.46|4.93 tcd|4.48|1.44x|1.10x| |H6144 T1 res w32|step~|10.50|12.61 lg|9.18|1.14x|1.37x| |H6144 T4 res w32|fwd~|2.75|2.56 lg|2.75|1.00x|0.93x| |H6144 T4 res w32|bwd~|6.05|6.14 tcd|4.48|1.35x|1.37x| |H6144 T4 res w32|step|10.46|12.58 lg|8.93|1.17x|1.41x| |H6144 T16 res w32|fwd|2.85|2.62 lg|2.85|1.00x|0.92x| |H6144 T16 res w32|bwd|6.75|8.22 tcd|6.72|1.00x|1.22x| |H6144 T16 res w32|step~|11.62|14.56 lg|11.81|0.98x|1.23x| |H6144 T64 res w32|fwd|3.14|2.88 lg|3.10|1.01x|0.93x| |H6144 T64 res w32|bwd~|7.10|8.90 tcd|7.23|0.98x|1.23x| |H6144 T64 res w32|step~|12.86|14.59 lg|12.90|1.00x|1.13x| |H6144 T256 res w32|fwd|4.51|4.32 lg|4.51|1.00x|0.96x| |H6144 T256 res w32|bwd|9.60|12.26 lg|9.34|1.03x|1.31x| |H6144 T256 res w32|step~|16.58|19.26 lg|17.09|0.97x|1.13x| |H6144 T1024 res w32|fwd|10.75|10.18 lg|10.82|0.99x|0.94x| |H6144 T1024 res w32|bwd|19.20|20.06 qa|16.51|1.16x|1.22x| |H6144 T1024 res w32|step|37.57|39.97 lg|36.16|1.04x|1.11x| |H6144 T4096 res w32|fwd|31.62|32.06 lg|31.60|1.00x|1.01x| |H6144 T4096 res w32|bwd|46.72|46.40 qa|44.10|1.06x|1.05x| |H6144 T4096 res w32|step|108.19|126.43 lg|104.93|1.03x|1.20x| |H6144 T14928 res w32|fwd|106.69|105.73 lg|106.27|1.00x|0.99x| |H6144 T14928 res w32|bwd|137.09|126.66 qa|129.78|1.06x|0.98x| |H6144 T14928 res w32|step|348.70|395.70 qa|340.42|1.02x|1.16x| |H6144 T16384 res w32|fwd|116.42|115.62 lg|116.38|1.00x|0.99x| |H6144 T16384 res w32|bwd|147.87|134.72 qa|139.31|1.06x|0.97x| |H6144 T16384 res w32|step|378.40|416.58 tc|368.96|1.03x|1.13x| |H6144 T32768 res w32|fwd|229.50|226.53 lg|229.28|1.00x|0.99x| |H6144 T32768 res w32|bwd|282.18|250.46 qa|260.26|1.08x|0.96x| |H6144 T32768 res w32|step|738.43|785.28 tc|716.45|1.03x|1.10x| |H6144 T65536 res w32|fwd|452.13|449.79 lg|452.61|1.00x|0.99x| |H6144 T65536 res w32|bwd|549.47|605.44 tc|500.42|1.10x|1.21x| |H6144 T65536 res w32|step|1450.85|1521.20 tc|1402.27|1.03x|1.08x| |[T,24,256] T1024|fwd~|6.24|5.98 tcd|6.24|1.00x|0.96x| |[T,24,256] T1024|bwd|14.77|24.37 tcd|15.39|0.96x|1.58x| |[T,24,256] T1024|step|23.17|33.57 tcd|23.97|0.97x|1.40x| |[T,24,256] T4096|fwd|17.22|17.09 tcd|17.18|1.00x|0.99x| |[T,24,256] T4096|bwd|32.38|42.46 tcd|37.86|0.86x|1.12x| |[T,24,256] T4096|step|61.73|69.92 tcd|66.82|0.92x|1.05x| |[T,24,256] T16384|fwd|59.94|60.26 tcd|59.94|1.00x|1.01x| |[T,24,256] T16384|bwd|99.94|114.82 tc|103.74|0.96x|1.11x| |[T,24,256] T16384|step|216.90|237.50 tc|221.79|0.98x|1.07x| |[T,24,256] T65536|fwd|227.26|229.73 lg|227.55|1.00x|1.01x| |[T,24,256] T65536|bwd|370.78|385.84 tcd|372.37|1.00x|1.04x| |[T,24,256] T65536|step|822.18|845.12 tcd|825.02|1.00x|1.02x| |[T,4,256] T1024|fwd|2.69|2.66 tcd|2.72|0.99x|0.98x| |[T,4,256] T1024|bwd~|7.94|9.12 tc|9.70|0.82x|0.94x| |[T,4,256] T1024|step~|12.26|14.46 tc|14.14|0.87x|1.02x| |[T,4,256] T4096|fwd|5.02|4.61 tcd|4.93|1.02x|0.94x| |[T,4,256] T4096|bwd|12.38|15.78 tcd|12.86|0.96x|1.23x| |[T,4,256] T4096|step|18.11|22.37 tcd|18.69|0.97x|1.20x| |[T,4,256] T16384|fwd|12.08|11.90 tc|12.19|0.99x|0.98x| |[T,4,256] T16384|bwd|24.86|34.53 tcd|25.41|0.98x|1.36x| |[T,4,256] T16384|step|42.85|53.95 tcd|43.52|0.98x|1.24x| |[T,4,256] T65536|fwd|41.23|40.83 tc|41.25|1.00x|0.99x| |[T,4,256] T65536|bwd|70.53|80.86 tc|73.82|0.96x|1.10x| |[T,4,256] T65536|step|151.04|159.49 tc|154.50|0.98x|1.03x| **R200 (sm_107a)** R200, 212 SMs, sm_107a, compute capability 10.7, driver 620.62, CUDA 13.4, torch 2.14.1+cu130. SM clock 2400-2424 MHz (median 2412), memory clock 4752 MHz, 4 GPUs of one node. This is a 212-SM R200 node. 216-SM R200 boards are timed separately and never pooled with it, and that measurement is pending. Rows: 78 shapes + 8 small-T shapes, x 3 ops = 258 rows. The small-T shapes are T1, T4, T16 and T64 of H6144 res and H6144 res w32. New and det meet the budget on every row. - `~`: 59 rows - `*`: 19 rows (listed below the table) | op | geomean vs det [min, max] | rows < 1 | geomean vs SOTA [min, max] | rows < 1 | | --- | --- | --- | --- | --- | | fwd (78) | 0.999x [0.957, 1.026] | 32 | 1.012x [0.871, 1.219] | 33 | | bwd (78) | 0.942x [0.537, 1.084] | 45 | 1.080x [0.645, 1.833] | 23 | | 2xfwd+bwd (78) | 0.971x [0.731, 1.056] | 50 | 1.096x [0.794, 1.581] | 16 | | fwd (small-T 8) | 0.994x [0.966, 1.000] | 3 | 0.903x [0.851, 0.987] | 8 | | bwd (small-T 8) | 1.005x [0.983, 1.019] | 3 | 0.758x [0.518, 0.936] | 8 | | 2xfwd+bwd (small-T 8) | 0.991x [0.949, 1.010] | 4 | 0.884x [0.703, 1.009] | 5 | | workload / shape / dtype / mode | operation | deterministic Cake latency (us) | non-Cake SOTA latency (us) | new non-deterministic Cake latency (us) | speedup vs deterministic Cake | speedup vs non-Cake SOTA | |---|---|---|---|---|---|---| |H512 T256|fwd~|2.02|1.98 tc|2.02|1.00x|0.98x| |H512 T256|bwd~|4.99|6.18 tc|4.96|1.01x|1.25x| |H512 T256|step~|8.29|9.95 tc|8.29|1.00x|1.20x| |H512 T1024|fwd|2.14|2.18 lg|2.14|1.00x|1.01x| |H512 T1024|bwd~|5.18|6.78 tc|5.15|1.01x|1.32x| |H512 T1024|step~|9.12|10.66 tc|9.06|1.01x|1.18x| |H512 T4096|fwd~|2.56|2.62 q|2.56|1.00x|1.02x| |H512 T4096|bwd~|6.94|8.45 tc|6.91|1.00x|1.22x| |H512 T4096|step~|11.78|12.96 tc|11.52|1.02x|1.13x| |H512 T14928|fwd~|4.13|4.13 tc|4.16|0.99x|0.99x| |H512 T14928|bwd~|10.88|17.02 qa|10.72|1.01x|1.59x| |H512 T14928|step~|18.34|24.83 tc|18.21|1.01x|1.36x| |H512 T16384|fwd~|4.45|4.45 tc|4.48|0.99x|0.99x| |H512 T16384|bwd~|11.04|16.93 tcd|10.94|1.01x|1.55x| |H512 T16384|step|19.04|26.18 tc|19.04|1.00x|1.37x| |H512 T32768|fwd|7.36|7.78 tc|7.46|0.99x|1.04x| |H512 T32768|bwd|15.46|21.95 qa|15.49|1.00x|1.42x| |H512 T32768|step|28.67|38.78 tc|28.93|0.99x|1.34x| |H512 T65536|fwd|12.74|12.86 tc|12.74|1.00x|1.01x| |H512 T65536|bwd|23.30|30.85 qa|23.36|1.00x|1.32x| |H512 T65536|step|47.97|58.27 tc|48.19|1.00x|1.21x| |H1536 T256|fwd|2.05|1.98 tc|2.05|1.00x|0.97x| |H1536 T256|bwd|5.31|6.05 tc|5.28|1.01x|1.15x| |H1536 T256|step|9.31|10.24 tc|8.99|1.04x|1.14x| |H1536 T1024|fwd~|2.40|2.40 qa|2.37|1.01x|1.01x| |H1536 T1024|bwd|6.08|7.14 tc|6.46|0.94x|1.10x| |H1536 T1024|step~|10.78|12.45 tc|11.01|0.98x|1.13x| |H1536 T4096|fwd~|3.78|3.78 tc|3.68|1.03x|1.03x| |H1536 T4096|bwd~|9.86|18.13 tcd|9.89|1.00x|1.83x| |H1536 T4096|step|16.10|25.50 tc|16.13|1.00x|1.58x| |H1536 T14928|fwd|9.34|10.34 q|9.47|0.99x|1.09x| |H1536 T14928|bwd|19.62|34.11 qa|19.71|1.00x|1.73x| |H1536 T14928|step|36.86|53.15 q|36.96|1.00x|1.44x| |H1536 T16384|fwd|9.76|11.10 q|9.89|0.99x|1.12x| |H1536 T16384|bwd~|20.83|29.70 tc|20.70|1.01x|1.43x| |H1536 T16384|step|39.20|49.79 tc|39.26|1.00x|1.27x| |H1536 T32768|fwd|17.79|18.59 tc|17.73|1.00x|1.05x| |H1536 T32768|bwd|34.18|45.05 tc|34.21|1.00x|1.32x| |H1536 T32768|step|69.54|78.62 tc|69.47|1.00x|1.13x| |H1536 T65536|fwd|32.74|33.28 tc|32.77|1.00x|1.02x| |H1536 T65536|bwd|60.51|68.24 tc|81.82|0.74x|0.83x| |H1536 T65536|step|126.08|133.92 tc|147.78|0.85x|0.91x| |H2048 T256|fwd~|2.05|1.98 qa|2.05|1.00x|0.97x| |H2048 T256|bwd~|5.28|6.56 tc|5.31|0.99x|1.23x| |H2048 T256|step~|9.22|11.10 tc|9.18|1.00x|1.21x| |H2048 T1024|fwd~|2.46|2.46 qa|2.46|1.00x|1.00x| |H2048 T1024|bwd|6.62|7.17 tc|6.40|1.03x|1.12x| |H2048 T1024|step|10.62|11.58 tc|10.50|1.01x|1.10x| |H2048 T4096|fwd~|4.32|4.35 tc|4.35|0.99x|1.00x| |H2048 T4096|bwd|10.98|18.59 tcd|10.85|1.01x|1.71x| |H2048 T4096|step|18.98|26.94 tc|19.04|1.00x|1.42x| |H2048 T14928|fwd|12.32|12.10 tc|12.29|1.00x|0.98x| |H2048 T14928|bwd|22.69|31.94 tc|22.59|1.00x|1.41x| |H2048 T14928|step|47.26|55.68 tc|47.20|1.00x|1.18x| |H2048 T16384|fwd|12.99|12.96 tc|12.96|1.00x|1.00x| |H2048 T16384|bwd|24.00|32.67 tc|24.00|1.00x|1.36x| |H2048 T16384|step|50.40|57.56 tc|50.21|1.00x|1.15x| |H2048 T32768|fwd|23.01|22.56 tc|23.17|0.99x|0.97x| |H2048 T32768|bwd|39.78|50.66 tc|39.94|1.00x|1.27x| |H2048 T32768|step|85.36|95.07 tc|85.70|1.00x|1.11x| |H2048 T65536|fwd|43.26|41.51 tc|43.20|1.00x|0.96x| |H2048 T65536|bwd|72.22|80.77 tc|89.09|0.81x|0.91x| |H2048 T65536|step|158.37|163.26 tc|176.10|0.90x|0.93x| |H4096 T256|fwd|2.30|2.14 lg|2.34|0.99x|0.92x| |H4096 T256|bwd|6.11|6.50 tc|6.18|0.99x|1.05x| |H4096 T256|step|10.21|10.62 tc|10.24|1.00x|1.04x| |H4096 T1024|fwd~|3.10|3.20 qa|3.04|1.02x|1.05x| |H4096 T1024|bwd|8.96|9.98 tc|9.12|0.98x|1.09x| |H4096 T1024|step|14.62|15.65 tc|14.75|0.99x|1.06x| |H4096 T4096|fwd|7.17|7.94 qa|7.14|1.00x|1.11x| |H4096 T4096|bwd|15.20|21.66 qa|15.10|1.01x|1.43x| |H4096 T4096|step|28.80|35.68 tc|28.99|0.99x|1.23x| |H4096 T14928|fwd|20.86|21.25 tc|21.02|0.99x|1.01x| |H4096 T14928|bwd|37.92|43.65 qa|37.89|1.00x|1.15x| |H4096 T14928|step|79.20|86.85 qa|79.20|1.00x|1.10x| |H4096 T16384|fwd|22.72|22.82 tc|22.85|0.99x|1.00x| |H4096 T16384|bwd|39.97|46.40 qa|40.22|0.99x|1.15x| |H4096 T16384|step|85.06|92.70 qa|85.24|1.00x|1.09x| |H4096 T32768|fwd|42.43|41.70 tc|42.56|1.00x|0.98x| |H4096 T32768|bwd|72.86|77.54 qa|69.70|1.05x|1.11x| |H4096 T32768|step|157.15|162.18 qa|153.95|1.02x|1.05x| |H4096 T65536|fwd|85.98|79.87 tc|85.83|1.00x|0.93x| |H4096 T65536|bwd*|132.38|151.84 tc|165.54|0.80x|0.92x| |H4096 T65536|step*|303.49|309.95 tc|337.12|0.90x|0.92x| |H5120 T256|fwd|2.40|2.37 qa|2.46|0.97x|0.96x| |H5120 T256|bwd|6.56|7.01 tc|6.59|1.00x|1.06x| |H5120 T256|step|11.17|11.58 tc|11.23|0.99x|1.03x| |H5120 T1024|fwd|3.49|3.55 qa|3.46|1.01x|1.03x| |H5120 T1024|bwd|10.18|10.88 tc|10.34|0.98x|1.05x| |H5120 T1024|step|16.19|17.30 tc|16.35|0.99x|1.06x| |H5120 T4096|fwd|8.64|9.63 qa|8.77|0.99x|1.10x| |H5120 T4096|bwd|19.65|24.38 qa|19.65|1.00x|1.24x| |H5120 T4096|step|36.35|43.07 qa|36.32|1.00x|1.19x| |H5120 T14928|fwd|25.95|26.24 qa|26.18|0.99x|1.00x| |H5120 T14928|bwd|44.83|50.66 qa|44.77|1.00x|1.13x| |H5120 T14928|step|95.94|102.53 qa|96.13|1.00x|1.07x| |H5120 T16384|fwd|28.29|28.29 qa|28.42|1.00x|1.00x| |H5120 T16384|bwd|47.49|53.73 qa|48.21|0.99x|1.11x| |H5120 T16384|step|103.68|110.27 qa|103.91|1.00x|1.06x| |H5120 T32768|fwd|52.70|51.90 qa|52.96|1.00x|0.98x| |H5120 T32768|bwd*|87.07|123.57 tc|86.11|1.01x|1.43x| |H5120 T32768|step*|191.94|241.25 tc|191.07|1.00x|1.26x| |H5120 T65536|fwd|110.56|100.42 qa|110.31|1.00x|0.91x| |H5120 T65536|bwd*|161.73|221.63 tc|300.86|0.54x|0.74x| |H5120 T65536|step*|381.09|448.00 tc|521.35|0.73x|0.86x| |H6144 T256|fwd~|2.82|2.50 qa|2.78|1.01x|0.90x| |H6144 T256|bwd|6.62|6.91 tc|6.78|0.98x|1.02x| |H6144 T256|step|11.36|11.74 tc|11.42|0.99x|1.03x| |H6144 T1024|fwd|3.97|3.97 qa|3.97|1.00x|1.00x| |H6144 T1024|bwd|10.62|12.16 tc|10.69|0.99x|1.14x| |H6144 T1024|step|18.27|20.32 tc|18.24|1.00x|1.11x| |H6144 T4096|fwd|9.98|11.23 qa|9.95|1.00x|1.13x| |H6144 T4096|bwd|22.40|26.18 qa|22.40|1.00x|1.17x| |H6144 T4096|step|41.66|48.32 qa|41.47|1.00x|1.17x| |H6144 T14928|fwd|30.18|30.78 qa|30.30|1.00x|1.02x| |H6144 T14928|bwd|52.42|55.85 qa|52.61|1.00x|1.06x| |H6144 T14928|step|113.07|117.25 qa|113.47|1.00x|1.03x| |H6144 T16384|fwd|32.96|33.30 qa|33.06|1.00x|1.01x| |H6144 T16384|bwd|56.32|59.78 qa|56.10|1.00x|1.07x| |H6144 T16384|step|121.73|125.12 qa|121.79|1.00x|1.03x| |H6144 T32768|fwd|62.78|62.69 qa|62.98|1.00x|1.00x| |H6144 T32768|bwd|101.82|104.70 qa|162.40|0.63x|0.64x| |H6144 T32768|step|226.82|228.70 qa|288.10|0.79x|0.79x| |H6144 T65536|fwd|122.88|120.06 qa|122.94|1.00x|0.98x| |H6144 T65536|bwd*|192.77|244.03 tc|311.11|0.62x|0.78x| |H6144 T65536|step*|438.11|486.18 tc|556.84|0.79x|0.87x| |H6144 T1 res|fwd~|2.40|2.37 tcd|2.40|1.00x|0.99x| |H6144 T1 res|bwd~|5.38|2.75 tc|5.31|1.01x|0.52x| |H6144 T1 res|step~|9.50|7.66 tc|10.02|0.95x|0.77x| |H6144 T4 res|fwd|2.59|2.37 lg|2.59|1.00x|0.91x| |H6144 T4 res|bwd~|5.38|5.12 tc|5.47|0.98x|0.94x| |H6144 T4 res|step~|10.24|10.24 tc|10.21|1.00x|1.00x| |H6144 T16 res|fwd|2.56|2.37 lg|2.56|1.00x|0.92x| |H6144 T16 res|bwd|5.54|4.35 tc|5.50|1.01x|0.79x| |H6144 T16 res|step~|9.82|9.12 tc|9.81|1.00x|0.93x| |H6144 T64 res|fwd|2.69|2.50 lg|2.69|1.00x|0.93x| |H6144 T64 res|bwd~|6.40|5.95 tc|6.43|1.00x|0.93x| |H6144 T64 res|step|10.94|11.10 tc|11.01|0.99x|1.01x| |H6144 T256 res|fwd|3.49|3.36 lg|3.49|1.00x|0.96x| |H6144 T256 res|bwd|7.97|8.03 tc|7.91|1.01x|1.02x| |H6144 T256 res|step|13.38|14.75 tc|13.50|0.99x|1.09x| |H6144 T1024 res|fwd|5.95|7.30 tc|5.98|0.99x|1.22x| |H6144 T1024 res|bwd~|13.70|13.06 tc|14.37|0.95x|0.91x| |H6144 T1024 res|step|24.70|27.68 tc|25.41|0.97x|1.09x| |H6144 T4096 res|fwd|18.30|18.82 tc|18.30|1.00x|1.03x| |H6144 T4096 res|bwd|32.90|29.95 qa|32.74|1.00x|0.91x| |H6144 T4096 res|step|68.42|73.54 tc|68.19|1.00x|1.08x| |H6144 T14928 res|fwd|56.54|60.96 tc|56.06|1.01x|1.09x| |H6144 T14928 res|bwd|84.45|69.70 qa|89.86|0.94x|0.78x| |H6144 T14928 res|step|195.71|217.54 qa|200.58|0.98x|1.08x| |H6144 T16384 res|fwd|61.41|64.93 tc|61.54|1.00x|1.06x| |H6144 T16384 res|bwd|92.42|74.85 qa|99.42|0.93x|0.75x| |H6144 T16384 res|step|213.89|220.05 tc|220.71|0.97x|1.00x| |H6144 T32768 res|fwd|119.42|130.88 tc|118.78|1.01x|1.10x| |H6144 T32768 res|bwd|169.89|133.60 qa|184.19|0.92x|0.73x| |H6144 T32768 res|step|407.71|415.20 tc|420.10|0.97x|0.99x| |H6144 T65536 res|fwd|234.72|258.59 tc|234.75|1.00x|1.10x| |H6144 T65536 res|bwd*|325.54|288.45 tc|352.19|0.92x|0.82x| |H6144 T65536 res|step|794.15|803.11 tc|820.39|0.97x|0.98x| |H5120 T256 w32|fwd|2.62|2.59 qa|2.62|1.00x|0.99x| |H5120 T256 w32|bwd~|7.07|7.81 tc|6.91|1.02x|1.13x| |H5120 T256 w32|step~|11.90|13.09 tc|11.55|1.03x|1.13x| |H5120 T1024 w32|fwd|3.74|3.71 qa|3.74|1.00x|0.99x| |H5120 T1024 w32|bwd~|10.78|11.07 tc|10.61|1.02x|1.04x| |H5120 T1024 w32|step~|16.86|18.98 tc|16.70|1.01x|1.14x| |H5120 T4096 w32|fwd~|8.90|10.59 qa|8.93|1.00x|1.19x| |H5120 T4096 w32|bwd|19.52|23.74 qa|19.58|1.00x|1.21x| |H5120 T4096 w32|step|36.42|43.10 qa|36.45|1.00x|1.18x| |H5120 T14928 w32|fwd|27.01|29.28 qa|26.75|1.01x|1.09x| |H5120 T14928 w32|bwd|45.22|49.70 qa|45.19|1.00x|1.10x| |H5120 T14928 w32|step|97.66|106.85 qa|97.60|1.00x|1.09x| |H5120 T16384 w32|fwd|28.93|31.71 qa|28.74|1.01x|1.10x| |H5120 T16384 w32|bwd|48.26|53.06 qa|48.13|1.00x|1.10x| |H5120 T16384 w32|step|104.48|115.20 qa|104.70|1.00x|1.10x| |H5120 T32768 w32|fwd|55.30|55.87 tc|54.98|1.01x|1.02x| |H5120 T32768 w32|bwd*|88.32|129.54 tc|87.30|1.01x|1.48x| |H5120 T32768 w32|step*|197.38|240.36 tc|196.26|1.01x|1.22x| |H5120 T65536 w32|fwd|107.39|104.70 tc|107.23|1.00x|0.98x| |H5120 T65536 w32|bwd*|163.33|233.66 tc|297.63|0.55x|0.79x| |H5120 T65536 w32|step*|375.07|441.67 tc|511.59|0.73x|0.86x| |H6144 T256 w32|fwd|2.91|2.75 qa|2.91|1.00x|0.95x| |H6144 T256 w32|bwd~|6.66|7.87 tc|6.69|1.00x|1.18x| |H6144 T256 w32|step~|11.23|12.51 tc|11.30|0.99x|1.11x| |H6144 T1024 w32|fwd|4.45|4.13 qa|4.45|1.00x|0.93x| |H6144 T1024 w32|bwd|10.56|12.70 tc|10.50|1.01x|1.21x| |H6144 T1024 w32|step|18.35|20.26 tc|18.34|1.00x|1.10x| |H6144 T4096 w32|fwd|9.82|10.85 qa|9.95|0.99x|1.09x| |H6144 T4096 w32|bwd|22.88|25.89 qa|22.69|1.01x|1.14x| |H6144 T4096 w32|step|42.11|46.98 qa|42.14|1.00x|1.11x| |H6144 T14928 w32|fwd|30.30|31.74 qa|30.27|1.00x|1.05x| |H6144 T14928 w32|bwd|53.63|56.58 qa|53.57|1.00x|1.06x| |H6144 T14928 w32|step|114.16|119.04 qa|113.89|1.00x|1.05x| |H6144 T16384 w32|fwd|33.12|34.46 qa|33.28|1.00x|1.04x| |H6144 T16384 w32|bwd|56.86|60.45 qa|56.96|1.00x|1.06x| |H6144 T16384 w32|step|123.07|128.61 qa|123.65|1.00x|1.04x| |H6144 T32768 w32|fwd|62.91|64.96 qa|62.78|1.00x|1.03x| |H6144 T32768 w32|bwd|102.06|105.12 qa|160.35|0.64x|0.66x| |H6144 T32768 w32|step|227.59|234.40 qa|286.14|0.80x|0.82x| |H6144 T65536 w32|fwd|123.11|123.87 tc|122.91|1.00x|1.01x| |H6144 T65536 w32|bwd*|194.24|248.93 tc|306.40|0.63x|0.81x| |H6144 T65536 w32|step*|439.49|496.10 tc|552.00|0.80x|0.90x| |H6144 T1 res w32|fwd~|2.69|2.37 tc|2.78|0.97x|0.85x| |H6144 T1 res w32|bwd~|5.22|2.78 tc|5.12|1.02x|0.54x| |H6144 T1 res w32|step~|9.63|6.82 tc|9.70|0.99x|0.70x| |H6144 T4 res w32|fwd~|2.85|2.46 lg|2.85|1.00x|0.87x| |H6144 T4 res w32|bwd~|5.47|4.35 tc|5.38|1.02x|0.81x| |H6144 T4 res w32|step|10.02|8.48 tc|9.92|1.01x|0.85x| |H6144 T16 res w32|fwd~|2.75|2.42 lg|2.75|1.00x|0.88x| |H6144 T16 res w32|bwd~|5.47|4.59 tc|5.50|0.99x|0.83x| |H6144 T16 res w32|step|10.02|8.58 tc|9.98|1.00x|0.86x| |H6144 T64 res w32|fwd~|2.94|2.62 lg|2.98|0.99x|0.88x| |H6144 T64 res w32|bwd~|6.43|5.28 tc|6.34|1.02x|0.83x| |H6144 T64 res w32|step~|11.38|11.70 tc|11.65|0.98x|1.00x| |H6144 T256 res w32|fwd|3.71|3.52 tc|3.74|0.99x|0.94x| |H6144 T256 res w32|bwd~|7.81|8.45 tc|7.74|1.01x|1.09x| |H6144 T256 res w32|step~|14.05|14.86 tc|14.14|0.99x|1.05x| |H6144 T1024 res w32|fwd|6.21|6.53 tc|6.14|1.01x|1.06x| |H6144 T1024 res w32|bwd|13.47|15.04 tc|14.21|0.95x|1.06x| |H6144 T1024 res w32|step|25.60|28.11 tc|26.18|0.98x|1.07x| |H6144 T4096 res w32|fwd|18.72|19.42 tc|18.62|1.01x|1.04x| |H6144 T4096 res w32|bwd|33.02|30.27 qa|32.61|1.01x|0.93x| |H6144 T4096 res w32|step|69.47|75.90 tc|69.18|1.00x|1.10x| |H6144 T14928 res w32|fwd|57.51|60.66 tc|57.22|1.01x|1.06x| |H6144 T14928 res w32|bwd|84.37|69.57 qa|89.39|0.94x|0.78x| |H6144 T14928 res w32|step|198.43|218.50 qa|202.34|0.98x|1.08x| |H6144 T16384 res w32|fwd|62.08|65.38 tc|62.02|1.00x|1.05x| |H6144 T16384 res w32|bwd|92.13|74.72 qa|99.10|0.93x|0.75x| |H6144 T16384 res w32|step|215.52|239.20 qa|221.38|0.97x|1.08x| |H6144 T32768 res w32|fwd|120.42|128.38 tc|120.29|1.00x|1.07x| |H6144 T32768 res w32|bwd|169.70|134.78 qa|183.45|0.93x|0.73x| |H6144 T32768 res w32|step|409.79|449.54 qa|422.75|0.97x|1.06x| |H6144 T65536 res w32|fwd|236.32|251.55 tc|235.97|1.00x|1.07x| |H6144 T65536 res w32|bwd*|326.66|399.33 tc|350.64|0.93x|1.14x| |H6144 T65536 res w32|step*|798.21|901.57 tc|821.35|0.97x|1.10x| |[T,24,256] T1024|fwd|4.32|4.03 tc|4.51|0.96x|0.89x| |[T,24,256] T1024|bwd~|13.98|17.25 tcd|13.79|1.01x|1.25x| |[T,24,256] T1024|step~|20.29|25.25 tc|20.26|1.00x|1.25x| |[T,24,256] T4096|fwd|10.08|10.11 tc|10.11|1.00x|1.00x| |[T,24,256] T4096|bwd~|24.16|29.73 tc|25.02|0.97x|1.19x| |[T,24,256] T4096|step|43.10|48.51 tc|44.29|0.97x|1.10x| |[T,24,256] T16384|fwd|34.73|33.44 tc|34.30|1.01x|0.97x| |[T,24,256] T16384|bwd|66.66|73.28 tc|71.33|0.93x|1.03x| |[T,24,256] T16384|step|136.58|139.39 tc|140.70|0.97x|0.99x| |[T,24,256] T65536|fwd|125.50|125.57 tc|125.62|1.00x|1.00x| |[T,24,256] T65536|bwd*|231.49|251.70 q|252.16|0.92x|1.00x| |[T,24,256] T65536|step*|484.40|783.52 q|504.90|0.96x|1.55x| |[T,4,256] T1024|fwd~|2.34|2.27 q|2.34|1.00x|0.97x| |[T,4,256] T1024|bwd~|8.26|7.26 tc|8.38|0.98x|0.87x| |[T,4,256] T1024|step~|13.15|11.74 tc|13.06|1.01x|0.90x| |[T,4,256] T4096|fwd~|3.74|3.23 tc|3.71|1.01x|0.87x| |[T,4,256] T4096|bwd|12.45|10.46 tc|11.49|1.08x|0.91x| |[T,4,256] T4096|step|17.68|15.89 tc|16.74|1.06x|0.95x| |[T,4,256] T16384|fwd|7.65|7.42 tc|7.74|0.99x|0.96x| |[T,4,256] T16384|bwd|19.65|24.54 tcd|20.67|0.95x|1.19x| |[T,4,256] T16384|step|31.55|41.83 tc|32.96|0.96x|1.27x| |[T,4,256] T65536|fwd|24.03|22.14 tc|23.97|1.00x|0.92x| |[T,4,256] T65536|bwd|47.62|50.72 tc|51.26|0.93x|0.99x| |[T,4,256] T65536|step|95.68|94.72 tc|98.91|0.97x|0.96x| `*` faster candidates outside the dw budget (us; dw err/tol): H4096 T65536 bwd qa 139.33 (1.246); H4096 T65536 step qa 300.19 (1.246); H5120 T32768 bwd qa 92.35, q 123.23 (1.478); H5120 T32768 step qa 195.39, q 239.23 (1.478); H5120 T65536 bwd qa 169.06 (1.355); H5120 T65536 step qa 367.87 (1.355); H6144 T65536 bwd qa 194.21, q 228.54 (2.290); H6144 T65536 step qa 432.74 (2.290); H6144 T65536 res bwd qa 252.51, q 284.64 (2.042); H5120 T32768 w32 bwd qa 90.98, q 121.38 (1.339); H5120 T32768 w32 step qa 204.58 (1.339); H5120 T65536 w32 bwd qa 165.82, q 227.26 (1.327); H5120 T65536 w32 step qa 383.01 (1.327); H6144 T65536 w32 bwd qa 194.75 (1.123); H6144 T65536 w32 step qa 446.31 (1.123); H6144 T65536 res w32 bwd qa 252.75, q 280.87 (1.751); H6144 T65536 res w32 step qa 868.56 (1.751); [T,24,256] T65536 bwd tc 238.02 (4.454); [T,24,256] T65536 step tc 488.99, tcd 639.19 (4.454/5.751). The family has no other variants: it ships these forms in both modes on sm_100a, sm_103a and sm_107a, and all three are measured above. <!-- This is an auto-generated comment: release notes by coderabbit.ai --> <!-- coderabbit-ai-generated:v1 --> ## Summary by CodeRabbit * **Performance Improvements** * Updated backward-pass execution for large hidden dimensions across supported GPU architectures. * Improved launch sizing to account for column-oriented work, including cases with small token counts. * **Reliability** * Expanded validation of numerical consistency and workspace handling across additional launch configurations. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Co-authored-by: Yingyi Huang <averyh@nvidia.com>
This was referenced Nov 6, 2026
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This PR adds the
cake_rmsnorm_trainpackage (flashinfer.cake_rmsnorm_train:cake_rmsnorm,cake_rmsnorm_train_forward,cake_rmsnorm_train_backward,cake_rmsnorm_train_backward_workspace_bytes,cake_rmsnorm_train_backward_workspace,CakeRMSNormFunction). These are the names the training RMSNorm used before the deterministic packagecake_rmsnorm_det_traintook thedetnames. The package covers BF16 activations with BF16 or FP32 weight, forward and backward, across 8 shape families: hidden sizes 512, 1536, 2048, 4096, 5120 and 6144, residual-add H 6144, and H 256 per-head views (query[T, 24, 256]with strides (12288, 512, 1); key[T, 4, 256]). Every entry point takesdeterministic, which defaults toTrueand returns the deterministic package's results. This PR delivers the opt-in non-deterministic backward (deterministic=False) for all of these variants. In that modedxis bitwise reproducible anddwis not. The forward anddeterministic=Truepaths run the deterministic package's programs.Speedup tables pending: the tables have one row per shape on B200, GB300 and R200 with absolute latencies. They compare against the deterministic Cake backward (
cake_rmsnorm_det_train) and the fastest measured non-Cake implementation, a static per-shapetorch.compile. They are being measured at this head and will be added before the PR leaves draft.The kernel's other Cake variants are the deterministic training RMSNorm
cake_rmsnorm_det_trainand the SiLU-gated training RMSNorm in deterministic (cake_rmsnorm_silu_gate_det_train) and non-deterministic (cake_rmsnorm_silu_gate_train) forms, and like this package they all ship on sm_100a (B200), sm_103a (GB300) and sm_107a (R200).