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build efinix: common: allow clk inverting on registered gpio
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allow clk inverting on registered gpio.

Signed-off-by: Fin Maaß <[email protected]>
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@maass-hamburg
maass-hamburg committed Sep 30, 2024
1 parent 0d0bfeb commit 0bd77b9
Showing 1 changed file with 20 additions and 20 deletions.
40 changes: 20 additions & 20 deletions litex/build/efinix/common.py
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Original file line number Diff line number Diff line change
Expand Up @@ -275,7 +275,7 @@ def lower(dr):
# Efinix DDRTristate -------------------------------------------------------------------------------

class EfinixDDRTristateImpl(LiteXModule):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, out_clk_inv=False, in_clk_inv=False):
assert oe1 == oe2
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
Expand Down Expand Up @@ -305,8 +305,8 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk,
"oe_reg" : "REG",
"in_clk_inv" : 0,
"out_clk_inv" : 0,
"in_clk_inv" : 1 if in_clk_inv else 0,
"out_clk_inv" : 1 if out_clk_inv else 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand All @@ -315,12 +315,12 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
class EfinixDDRTristate:
@staticmethod
def lower(dr):
return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, **dr.kwargs)

# Efinix SDRTristate -------------------------------------------------------------------------------

class EfinixSDRTristateImpl(LiteXModule):
def __init__(self, io, o, oe, i, clk):
def __init__(self, io, o, oe, i, clk, out_clk_inv=False, in_clk_inv=False):
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
io_name = platform.get_pin_name(io)
Expand All @@ -345,8 +345,8 @@ def __init__(self, io, o, oe, i, clk):
"out_reg" : "REG",
"out_clk_pin" : clk,
"oe_reg" : "REG",
"in_clk_inv" : 0,
"out_clk_inv" : 0,
"in_clk_inv" : 1 if in_clk_inv else 0,
"out_clk_inv" : 1 if out_clk_inv else 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand All @@ -356,12 +356,12 @@ def __init__(self, io, o, oe, i, clk):
class EfinixSDRTristate(LiteXModule):
@staticmethod
def lower(dr):
return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, **dr.kwargs)

# Efinix SDROutput ---------------------------------------------------------------------------------

class EfinixSDROutputImpl(LiteXModule):
def __init__(self, i, o, clk):
def __init__(self, i, o, clk, out_clk_inv=False):
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
io_name = platform.get_pin_name(o)
Expand All @@ -379,7 +379,7 @@ def __init__(self, i, o, clk):
"size" : 1,
"out_reg" : "REG",
"out_clk_pin" : clk,
"out_clk_inv" : 0,
"out_clk_inv" : 1 if out_clk_inv else 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand All @@ -389,12 +389,12 @@ def __init__(self, i, o, clk):
class EfinixSDROutput(LiteXModule):
@staticmethod
def lower(dr):
return EfinixSDROutputImpl(dr.i, dr.o, dr.clk)
return EfinixSDROutputImpl(dr.i, dr.o, dr.clk, **dr.kwargs)

# Efinix DDROutput ---------------------------------------------------------------------------------

class EfinixDDROutputImpl(LiteXModule):
def __init__(self, i1, i2, o, clk):
def __init__(self, i1, i2, o, clk, out_clk_inv=False):
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
io_name = platform.get_pin_name(o)
Expand All @@ -414,7 +414,7 @@ def __init__(self, i1, i2, o, clk):
"size" : 1,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk,
"out_clk_inv" : 0,
"out_clk_inv" : 1 if out_clk_inv else 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand All @@ -423,12 +423,12 @@ def __init__(self, i1, i2, o, clk):
class EfinixDDROutput:
@staticmethod
def lower(dr):
return EfinixDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
return EfinixDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk, **dr.kwargs)

# Efinix SDRInput ----------------------------------------------------------------------------------

class EfinixSDRInputImpl(LiteXModule):
def __init__(self, i, o, clk):
def __init__(self, i, o, clk, in_clk_inv=False):
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
io_name = platform.get_pin_name(i)
Expand All @@ -445,20 +445,20 @@ def __init__(self, i, o, clk):
"size" : 1,
"in_reg" : "REG",
"in_clk_pin" : clk,
"in_clk_inv" : 0
"in_clk_inv" : 1 if in_clk_inv else 0,
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(platform.get_pin(i))

class EfinixSDRInput:
@staticmethod
def lower(dr):
return EfinixSDRInputImpl(dr.i, dr.o, dr.clk)
return EfinixSDRInputImpl(dr.i, dr.o, dr.clk, **dr.kwargs)

# Efinix DDRInput ----------------------------------------------------------------------------------

class EfinixDDRInputImpl(LiteXModule):
def __init__(self, i, o1, o2, clk):
def __init__(self, i, o1, o2, clk, in_clk_inv=False):
assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform
io_name = platform.get_pin_name(i)
Expand All @@ -477,15 +477,15 @@ def __init__(self, i, o1, o2, clk):
"size" : 1,
"in_reg" : "DDIO_RESYNC",
"in_clk_pin" : clk,
"in_clk_inv" : 0
"in_clk_inv" : 1 if in_clk_inv else 0,
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(platform.get_pin(i))

class EfinixDDRInput:
@staticmethod
def lower(dr):
return EfinixDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
return EfinixDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk, **dr.kwargs)

# Efinix Special Overrides -------------------------------------------------------------------------

Expand Down

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