build: efinix: EfinixClkOutput: allow inverting

allow inverting of EfinixClkOutput.

Signed-off-by: Fin Maaß <[email protected]>

litex/build/efinix/common.py

@@ -109,7 +109,7 @@ def lower(dr):
 # Efinix Clk Output --------------------------------------------------------------------------------
 
 class EfinixClkOutputImpl(LiteXModule):
-    def __init__(self, i, o):
+    def __init__(self, i, o, out_clk_inv=False):
         assert_is_signal_or_clocksignal(i)
         platform = LiteXContext.platform
         block = {
@@ -119,14 +119,15 @@ def __init__(self, i, o):
             "properties" : platform.get_pin_properties(o),
             "name"       : i,
             "mode"       : "OUTPUT_CLK",
+            "out_clk_inv": 1 if out_clk_inv else 0,
         }
         platform.toolchain.ifacewriter.blocks.append(block)
         platform.toolchain.excluded_ios.append(o)
 
 class EfinixClkOutput(LiteXModule):
     @staticmethod
     def lower(dr):
-        return EfinixClkOutputImpl(dr.i, dr.o)
+        return EfinixClkOutputImpl(dr.i, dr.o, **dr.kwargs)
 
 # Efinix Tristate ----------------------------------------------------------------------------------
 

litex/build/efinix/ifacewriter.py

@@ -275,6 +275,8 @@ def generate_gpio(self, block, verbose=True):
             cmd += 'design.create_clockout_gpio("{}")\n'.format(name)
             cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, name)
             cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block["location"])
+            if "out_clk_inv" in block:
+                cmd += f'design.set_property("{name}","IS_OUTCLK_INVERTED","{block["out_clk_inv"]}")\n'
             if prop:
                 for p, val in prop:
                     cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)