[RyuJIT] Enable contained form for shlx, sarx, shrx and on x86

[JulieLeeMSFT]

Related to #41881.

#67182 handles non contained form of shifts such that all three operands are registers.
Extend it to support contained form based on this comment.

More complex changes being needed in the emitter.

Ideally we'd fix up the emitter and use inst_RV_RV_TT instead so that we can emit shlx r32a, r/m32, r32b. Someone would need to walk through the relevant IF_RWR_RRD_*RD formats and ensure that it's all handled correctly (noting that technically the format is IF_RWR_*RD_RRD but that should be the same as IF_RWR_RRD_*RD with swapping op1/op2, like we do for a couple other BMI2 instructions, namely bextr and bzhi.

Edit: Also, enable emitting the three instructions on x86. Need to check lsraxarch and emitter part.

category:implementation
theme:basic-cq
skill-level:intermediate
cost:medium
impact:medium

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Issue Details

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Related to #41881.

#67182 handles non contained form of shifts such that all three operands are registers.
Extend it to support contained form based on this comment.

More complex changes being needed in the emitter.

Ideally we'd fix up the emitter and use inst_RV_RV_TT instead so that we can emit shlx r32a, r/m32, r32b. Someone would need to walk through the relevant IF_RWR_RRD_*RD formats and ensure that it's all handled correctly (noting that technically the format is IF_RWR_*RD_RRD but that should be the same as IF_RWR_RRD_*RD with swapping op1/op2, like we do for a couple other BMI2 instructions, namely bextr and bzhi.

Author:	JulieLeeMSFT
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	Future

[JulieLeeMSFT]

cc @dotnet/jit-contrib.

[BruceForstall]

IMO, you should create a separate issue to track enabling for x86, and make this one just about memory containment.