New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Verilog: use zero_extend_exprt #796

Draft

kroening wants to merge 1 commit into main from zero-extend

Member

kroening commented Nov 1, 2024

This replaces two typecasts by zero_extend_exprt.


          Verilog: use zero_extend_exprt

f23e09c

This replaces two typecasts by zero_extend_exprt.

kroening added the Verilog label

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels