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Pull requests: diffblue/hw-cbmc

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Pull requests list

SVA/LTL property instrumentation engines
#797 opened Nov 3, 2024 by kroening • Draft
Verilog: use zero_extend_exprt Verilog
#796 opened Nov 1, 2024 by kroening • Draft
word-level BMC: add missing SVA expressions Verilog
#759 opened Oct 9, 2024 by kroening • Draft
Verilog: default aval/bval lowering Verilog
#668 opened Sep 5, 2024 by kroening • Draft
Verilog: expr2verilog can now decode aval/bval constants Verilog
#570 opened Jun 22, 2024 by kroening • Draft
SAT-based neural ranking engine engines
#524 opened May 27, 2024 by kroening Loading…
SystemVerilog: implement package import Verilog
#483 opened May 5, 2024 by kroening • Draft
Verilog: fix for indexed part select Verilog
#424 opened Mar 21, 2024 by kroening • Draft
ebmc: HWMCC 2017 benchmarks in CI
#387 opened Feb 29, 2024 by kroening Loading…
2
add AIGER frontend
#383 opened Feb 28, 2024 by kroening • Draft
netlistt: remove dependency on var_mapt
#382 opened Feb 28, 2024 by kroening • Draft
nuterm using libtorch engines
#328 opened Jan 3, 2024 by kroening Loading…
@tautschnig
Verilog: add symbols below generate-if Verilog
#318 opened Dec 24, 2023 by kroening • Draft
ebmc: liveness to safety with IC3 engines
#285 opened Dec 11, 2023 by kroening • Draft
nuTerm for VCDs engines
#243 opened Dec 4, 2023 by tautschnig • Draft
Sort definitions of SMV models to reduce recursion depth in typecheck
#234 opened Dec 3, 2023 by mgudemann Loading…
1
3
ebmc CEGAR engines
#133 opened Oct 18, 2023 by kroening • Draft
Bugfix/languaget gets message handler
#31 opened Sep 13, 2017 by mgudemann Loading…
2
Sort definitions topologically before doing typecheck for SMV
#26 opened Jul 5, 2017 by mgudemann Loading…
1
1
Replacing C-like input/output with C++ style code, some other changes
#22 opened Jul 3, 2017 by eigold Loading…
28
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