Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

formatter doesn't allow named arguments to be on separate lines? #2339

Open
gobbedy opened this issue Jan 21, 2025 · 4 comments
Open

formatter doesn't allow named arguments to be on separate lines? #2339

gobbedy opened this issue Jan 21, 2025 · 4 comments
Labels
formatter Verilog code formatter issues

Comments

@gobbedy
Copy link

gobbedy commented Jan 21, 2025

Hello, is there any way to get the formatter to keep the original formatting below? I think I tried every option and nothing worked.

To be clear, we WANT the original formatting (with one argument per line) but the formatter is forcing the actual output, seemingly regardless of what options I set.

Thanks in advance!

Test case

class my_class;

   function void my_func();

      // --------------------------------
      my_func(      .arg1(`TB_AEOH), 
                          .arg2(1),
                          .arg3(1),
                          .arg4(1),
                          .arg5(1),
                          .arg6(1),
                          .arg7(1),
                          .arg8(1),
                          .arg9(1),
                          .arg10(1),
                          .arg11(12),
                          .arg12(8),
                          .arg13(50)
                        );

   endfunction

endclass

Include any options or configuration used.

Actual output

class my_class;

  function void my_func();

    // --------------------------------
    my_func(.arg1(`TB_AEOH), .arg2(1), .arg3(1), .arg4(1), .arg5(1), .arg6(1), .arg7(1), .arg8(1),
            .arg9(1), .arg10(1), .arg11(12), .arg12(8), .arg13(50));

  endfunction

endclass
@gobbedy gobbedy added the formatter Verilog code formatter issues label Jan 21, 2025
@hzeller
Copy link
Collaborator

hzeller commented Jan 21, 2025

looks like currently there is not an option yet for the formatter (such as --named_parameter_indentation=indent) that applies to function calls not module instantiations.

So for now I suggest to wrap the part of the code in // verilog_format: off and on

https://github.com/chipsalliance/verible/tree/master/verible/verilog/tools/formatter#disabling-formatting-disable-formatting

@gobbedy
Copy link
Author

gobbedy commented Jan 22, 2025

@hzeller thank you, will do

@fangism
Copy link
Collaborator

fangism commented Jan 23, 2025

In general, one can force line separations by adding trailing // comments (even if empty) to desired lines, but I understand that is not always a reasonable solution.

@gobbedy
Copy link
Author

gobbedy commented Jan 30, 2025

@fangism thank you, that is a useful workaround to keep in mind

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
formatter Verilog code formatter issues
Projects
None yet
Development

No branches or pull requests

3 participants