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Incorrect wrap with comma at interface declaration and enum #2331

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BrianLChen opened this issue Jan 16, 2025 · 0 comments
Open

Incorrect wrap with comma at interface declaration and enum #2331

BrianLChen opened this issue Jan 16, 2025 · 0 comments
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formatter Verilog code formatter issues

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@BrianLChen
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BrianLChen commented Jan 16, 2025

Test case

module test (
  input logic clk, nrst,

  output logic [7:0] count, count2,
  output logic count_max
);

typedef enum {state1, state2, state3} state_t;

Actual output

module test (
    input logic clk,
    nrst,

    output logic [7:0] count,
    count2,
    output logic count_max
);

  typedef enum {
    state1,
    state2,
    state3
  } state_t;

Expected or suggested output

module test (
  input logic clk, nrst,

  output logic [7:0] count, count2,
  output logic count_max
);

  typedef enum {state1, state2, state3} state_t;

The interface (port) with the same input logic/output logic statement should be placed on the same line. The comma used in enum is also been affected.

@BrianLChen BrianLChen added the formatter Verilog code formatter issues label Jan 16, 2025
@BrianLChen BrianLChen changed the title Incorrect wrap at interface declaration Incorrect wrap with comma at interface declaration and enum Jan 17, 2025
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Labels
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