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It Can NOT preprocess properly in SystemVerilog files? #2217

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zpxy opened this issue Jul 17, 2024 · 1 comment
Open

It Can NOT preprocess properly in SystemVerilog files? #2217

zpxy opened this issue Jul 17, 2024 · 1 comment
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style-linter Verilog style-linter issues

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@zpxy
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zpxy commented Jul 17, 2024 •
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Describe the bug
I use a gloabal "define" file and "macro" file to manager all parameters and macros, but verible-verilog_lint can't recongnize the macro in other file , it say an error: error in expanding the macro , might not be difined before
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so would you plan to solve the preprocess problem?
@zpxy zpxy added the style-linter Verilog style-linter issues label Jul 17, 2024
@hzeller
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hzeller commented Jul 17, 2024

Yes, preprocessor does need some work. It is fairly high on my list, but unfortunately there are other projects also competing for my attention.

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@hzeller @zpxy