Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

What is the current state of spaces in the preprocessor #2183

Open
The-MEO opened this issue May 22, 2024 · 0 comments
Open

What is the current state of spaces in the preprocessor #2183

The-MEO opened this issue May 22, 2024 · 0 comments
Labels
rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).

Comments

@The-MEO
Copy link

The-MEO commented May 22, 2024

Describe the bug

Is it correct, that the preprocessor removes all spaces from defines?

To Reproduce

`define SVTEST(_NAME_) task automatic TEST_GITHUB();
`define SVTEST_END endtask

module github_issue;
`SVTEST(get_root)
`SVTEST_END
endmodule

Command to execute verible-verilog-preprocessor preprocess github.sv

Actual behavior:

`defineSVTEST(_NAME_)task automatic TEST_GITHUB();
`defineSVTEST_ENDendtask

module github_issue;
taskautomaticTEST_GITHUB();
endtask
endmodule

Expected behavior

I would expect that the spaces are preserved in define's after reading #1528.

`define SVTEST(_NAME_) task automatic TEST_GITHUB();
`define SVTEST_END endtask

module github_issue;
task automatic TEST_GITHUB();
endtask
endmodule
@The-MEO The-MEO added the rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017). label May 22, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
Projects
None yet
Development

No branches or pull requests

1 participant