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catch None.get in BitPat.apply(x: UInt): BitPat #2276

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Merged
merged 4 commits into from
Dec 9, 2021
Merged

catch None.get in BitPat.apply(x: UInt): BitPat #2276

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8a2292b
catch None.get in BitPat.apply(x: UInt): BitPat
sequencer Dec 2, 2021
7786ccf
Update src/main/scala/chisel3/util/BitPat.scala
jackkoenig Dec 9, 2021
15bbbd0
Apply suggestions from code review
jackkoenig Dec 9, 2021
30923ee
Merge branch 'master' into bitpat_fix
mergify[bot] Dec 9, 2021
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2 changes: 1 addition & 1 deletion src/main/scala/chisel3/util/BitPat.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ object BitPat {
*/
def apply(x: UInt): BitPat = {
val len = if (x.isWidthKnown) x.getWidth else 0
apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
apply("b" + x.litOption.getOrElse(throw new ChiselException(s"$x is not a literal, BitPat.apply(x: UInt) only accept literal")).toString(2).reverse.padTo(len, "0").reverse.mkString)
}

implicit class fromUIntToBitPatComparable(x: UInt) extends SourceInfoDoc {
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8 changes: 8 additions & 0 deletions src/test/scala/chiselTests/util/BitPatSpec.scala
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Expand Up @@ -28,6 +28,14 @@ class BitPatSpec extends AnyFlatSpec with Matchers {
(BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)")
}

it should "throw when BitPat apply to a Hardware" in {
intercept[chisel3.internal.ChiselException]{
chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module {
BitPat(chisel3.Reg(chisel3.Bool()))
})
}
}

it should "index and return new BitPat" in {
val b = BitPat("b1001???")
b(0) should be(BitPat.dontCare(1))
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