Issue #831: Fix compile issues on MinGW

[hs-apotell]

Issue actions/runner-images#831: Fix compile issues on MinGW

• Use WIN32_LEAN_AND_MEAN when building on Windows to avoid pulling in irrelevant headers
• Rename "interface" to "interface_inst" to avoid conflicting with system defined class with the same name.
• Rename "module" to "module_inst" since the latter is now a C++ reserved word as of C++ 20.

[hs-apotell]

The mac build failure is fixed by actions/runner-images#846. It's a CI runner image issue and not specific to Surelog or UHDM.

[alaindargelas]

@hs-apotell, I'm just realizing now what changed here.
There was no reason to change vpiModule into vpiModuleInst. Same with vpiInstance,. These are the STANDARD Verilog object model names. They pose no issue to the MinGW compiler....
Please submit a PR ASAP to revert back to vpiModule and vpiInstance.
The "module" class can be changed to module_inst, but not the vpiModule name which is in the standard.

There was no mention of the changes you made in the vpi_user.h in the explanation above.

Please do not change the content of vpi_user.h or sv_vpi_user.h without an explicit discussion. These are standard files.

[alaindargelas]

I opened #859