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Enable the RISCVC mode #1594

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garrettgu10 wants to merge 1 commit into from
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Enable the RISCVC mode #1594

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14 changes: 8 additions & 6 deletions arch/RISCV/RISCVDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,19 +37,21 @@

/* When we specify the RISCV64 mode, It means It is RV64IMAFD.
Similar, RISCV32 means RV32IMAFD.
When the RISCVC mode is also specified, we should enable the compression feature
*/
static uint64_t getFeatureBits(int mode)
{
if (mode == CS_MODE_RISCV32)
// return b11110
if (mode & CS_MODE_RISCV32)
// return b111010, with 2nd bit reflecting C
return RISCV_FeatureStdExtM | RISCV_FeatureStdExtA |
RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ;
RISCV_FeatureStdExtF | RISCV_FeatureStdExtD |
(mode & CS_MODE_RISCVC ? RISCV_FeatureStdExtC: 0l) ;
else

// CS_MODE_RISCV64, return b11111
// CS_MODE_RISCV64, return b111011, with 2nd bit reflecting C
return RISCV_Feature64Bit | RISCV_FeatureStdExtM |
RISCV_FeatureStdExtA | RISCV_FeatureStdExtF |
RISCV_FeatureStdExtD ;
RISCV_FeatureStdExtD |
(mode & CS_MODE_RISCVC ? RISCV_FeatureStdExtC: 0l) ;
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@rth7680 rth7680 Sep 12, 2020

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I think it would be cleaner to not try to put everything on one line. E.g.

    uint64_t ret = M | A | F | D;
    if (mode & CS_MODE_RISCV64)
        ret |= 64Bit;
    if (mode & CD_MODE_RISCVC)
        ret |= C;
    return ret;

}

#define GET_REGINFO_ENUM
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