Enable the RISCVC mode #1594
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Enable the RISCVC mode #1594
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Right now, it seems like the CS_MODE_RISCVC mode is not used anywhere in the RISCV backend. We should enable or disable the compressed instructions based on whether or not the CS_MODE_RISCVC mode is specified.
Author
|
Can you please review this? Thank you! |
rth7680
reviewed
Sep 12, 2020
| RISCV_FeatureStdExtA | RISCV_FeatureStdExtF | | ||
| RISCV_FeatureStdExtD ; | ||
| RISCV_FeatureStdExtD | | ||
| (mode & CS_MODE_RISCVC ? RISCV_FeatureStdExtC: 0l) ; |
Contributor
There was a problem hiding this comment.
I think it would be cleaner to not try to put everything on one line. E.g.
uint64_t ret = M | A | F | D;
if (mode & CS_MODE_RISCV64)
ret |= 64Bit;
if (mode & CD_MODE_RISCVC)
ret |= C;
return ret;
Merged
Collaborator
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can you look at #1682? if that is merged, this PR is not necessary anymore. |
Collaborator
|
close this since we merged the other one, thanks! |
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Right now, it seems like the CS_MODE_RISCVC mode is not used anywhere in the RISCV backend. We should enable or disable the compressed instructions based on whether or not the CS_MODE_RISCVC mode is specified.