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Updates files from LLVM for PPC64 #1510

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Merged
aquynh merged 2 commits into from
Jul 1, 2019
Merged

Updates files from LLVM for PPC64 #1510

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8681eca
Updates files from LLVM for PPC64
catenacyber Jun 26, 2019
41476e7
Only fix tbegin, tabort and such
catenacyber Jun 27, 2019
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38 changes: 18 additions & 20 deletions suite/synctools/tablegen/PPC/PPCInstrHTM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -21,69 +21,71 @@ def HTM_get_imm : SDNodeXForm<imm, [{
}]>;

let hasSideEffects = 1, usesCustomInserter = 1 in {
def TCHECK_RET : Pseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>;
def TCHECK_RET : Pseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>;
def TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>;
}


let Predicates = [HasHTM] in {

let Defs = [CR0] in {
def TBEGIN : XForm_htm0 <31, 654,
(outs crrc0:$ret), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
(outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;

def TEND : XForm_htm1 <31, 686,
(outs crrc0:$ret), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
(outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;

def TABORT : XForm_base_r3xo <31, 910,
(outs crrc0:$ret), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
(outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
[]>, isDOT {
let RST = 0;
let B = 0;
}

def TABORTWC : XForm_base_r3xo <31, 782,
(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B),
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
"tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>,
isDOT;

def TABORTWCI : XForm_base_r3xo <31, 846,
(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
"tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>,
isDOT;

def TABORTDC : XForm_base_r3xo <31, 814,
(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B),
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
"tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>,
isDOT;

def TABORTDCI : XForm_base_r3xo <31, 878,
(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
"tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>,
isDOT;

def TSR : XForm_htm2 <31, 750,
(outs crrc0:$ret), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
(outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
isDOT;

def TCHECK : XForm_htm3 <31, 718,
(outs), (ins crrc:$BF), "tcheck $BF", IIC_SprMTSPR, []>;


def TRECLAIM : XForm_base_r3xo <31, 942,
(outs crrc:$ret), (ins gprc:$A), "treclaim. $A",
(outs), (ins gprc:$A), "treclaim. $A",
IIC_SprMTSPR, []>,
isDOT {
let RST = 0;
let B = 0;
}

def TRECHKPT : XForm_base_r3xo <31, 1006,
(outs crrc:$ret), (ins), "trechkpt.", IIC_SprMTSPR, []>,
(outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,
isDOT {
let RST = 0;
let A = 0;
let B = 0;
}

}//Defs = [CR0]

def TCHECK : XForm_htm3 <31, 718,
(outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR, []>;
// Builtins

// All HTM instructions, with the exception of tcheck, set CR0 with the
Expand All @@ -94,15 +96,11 @@ def TRECHKPT : XForm_base_r3xo <31, 1006,
// tbegin builtin API which defines a return value of 1 as success.

def : Pat<(int_ppc_tbegin i32:$R),
(XORI
(EXTRACT_SUBREG (
TBEGIN (HTM_get_imm imm:$R)), sub_eq),
1)>;
(XORI (TBEGIN_RET(HTM_get_imm imm:$R)), 1)>;

def : Pat<(int_ppc_tend i32:$R),
(TEND (HTM_get_imm imm:$R))>;


def : Pat<(int_ppc_tabort i32:$R),
(TABORT $R)>;

Expand Down
4 changes: 0 additions & 4 deletions suite/synctools/tablegen/PPC/PPCInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -540,10 +540,6 @@ def PPCRegCRRCAsmOperand : AsmOperandClass {
def crrc : RegisterOperand<CRRC> {
let ParserMatchClass = PPCRegCRRCAsmOperand;
}
def crrc0 : RegisterOperand<CRRC0> {
let ParserMatchClass = PPCRegCRRCAsmOperand;
}

def PPCRegSPERCAsmOperand : AsmOperandClass {
let Name = "RegSPERC"; let PredicateMethod = "isRegNumber";
}
Expand Down
2 changes: 0 additions & 2 deletions suite/synctools/tablegen/PPC/PPCRegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -369,8 +369,6 @@ def CRBITRC : RegisterClass<"PPC", [i1], 32,
def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
CR7, CR2, CR3, CR4)>;

def CRRC0 : RegisterClass<"PPC", [i32], 32, (add CR0)>;

// The CTR registers are not allocatable because they're used by the
// decrement-and-branch instructions, and thus need to stay live across
// multiple basic blocks.
Expand Down