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winch: Use Reg where appropriate in the Masm #7002

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Sep 12, 2023
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winch: Use Reg where appropriate in the Masm #7002

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32 changes: 11 additions & 21 deletions winch/codegen/src/codegen/context.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -150,11 +150,11 @@ impl<'a> CodeGenContext<'a> {
pub fn move_val_to_reg<M: MacroAssembler>(&self, src: &Val, dst: Reg, masm: &mut M) {
let size: OperandSize = src.ty().into();
match src {
Val::Reg(tr) => masm.mov(RegImm::reg(tr.reg), RegImm::reg(dst), size),
Val::I32(imm) => masm.mov(RegImm::i32(*imm), RegImm::reg(dst), size),
Val::I64(imm) => masm.mov(RegImm::i64(*imm), RegImm::reg(dst), size),
Val::F32(imm) => masm.mov(RegImm::f32(imm.bits()), RegImm::reg(dst), size),
Val::F64(imm) => masm.mov(RegImm::f64(imm.bits()), RegImm::reg(dst), size),
Val::Reg(tr) => masm.mov(RegImm::reg(tr.reg), dst, size),
Val::I32(imm) => masm.mov(RegImm::i32(*imm), dst, size),
Val::I64(imm) => masm.mov(RegImm::i64(*imm), dst, size),
Val::F32(imm) => masm.mov(RegImm::f32(imm.bits()), dst, size),
Val::F64(imm) => masm.mov(RegImm::f64(imm.bits()), dst, size),
Val::Local(local) => {
let slot = self
.frame
Expand Down Expand Up @@ -184,7 +184,7 @@ impl<'a> CodeGenContext<'a> {
/// Prepares arguments for emitting an i32 binary operation.
pub fn i32_binop<F, M>(&mut self, masm: &mut M, mut emit: F)
where
F: FnMut(&mut M, RegImm, RegImm, OperandSize),
F: FnMut(&mut M, Reg, RegImm, OperandSize),
M: MacroAssembler,
{
let top = self.stack.peek().expect("value at stack top");
Expand All @@ -195,17 +195,12 @@ impl<'a> CodeGenContext<'a> {
.pop_i32_const()
.expect("i32 const value at stack top");
let typed_reg = self.pop_to_reg(masm, None);
emit(
masm,
RegImm::reg(typed_reg.reg),
RegImm::i32(val),
OperandSize::S32,
);
emit(masm, typed_reg.reg, RegImm::i32(val), OperandSize::S32);
self.stack.push(typed_reg.into());
} else {
let src = self.pop_to_reg(masm, None);
let dst = self.pop_to_reg(masm, None);
emit(masm, dst.reg.into(), src.reg.into(), OperandSize::S32);
emit(masm, dst.reg, src.reg.into(), OperandSize::S32);
self.free_reg(src);
self.stack.push(dst.into());
}
Expand All @@ -214,7 +209,7 @@ impl<'a> CodeGenContext<'a> {
/// Prepares arguments for emitting an i64 binary operation.
pub fn i64_binop<F, M>(&mut self, masm: &mut M, mut emit: F)
where
F: FnMut(&mut M, RegImm, RegImm, OperandSize),
F: FnMut(&mut M, Reg, RegImm, OperandSize),
M: MacroAssembler,
{
let top = self.stack.peek().expect("value at stack top");
Expand All @@ -224,17 +219,12 @@ impl<'a> CodeGenContext<'a> {
.pop_i64_const()
.expect("i64 const value at stack top");
let typed_reg = self.pop_to_reg(masm, None);
emit(
masm,
RegImm::reg(typed_reg.reg),
RegImm::i64(val),
OperandSize::S64,
);
emit(masm, typed_reg.reg, RegImm::i64(val), OperandSize::S64);
self.stack.push(typed_reg.into());
} else {
let src = self.pop_to_reg(masm, None);
let dst = self.pop_to_reg(masm, None);
emit(masm, dst.reg.into(), src.reg.into(), OperandSize::S64);
emit(masm, dst.reg, src.reg.into(), OperandSize::S64);
self.free_reg(src);
self.stack.push(dst.into());
}
Expand Down
49 changes: 17 additions & 32 deletions winch/codegen/src/isa/aarch64/masm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -147,9 +147,9 @@ impl Masm for MacroAssembler {
self.asm.finalize()
}

fn mov(&mut self, src: RegImm, dst: RegImm, size: OperandSize) {
fn mov(&mut self, src: RegImm, dst: Reg, size: OperandSize) {
match (src, dst) {
(RegImm::Imm(v), RegImm::Reg(rd)) => {
(RegImm::Imm(v), rd) => {
let imm = match v {
I::I32(v) => v as u64,
I::I64(v) => v,
Expand All @@ -160,20 +160,19 @@ impl Masm for MacroAssembler {
self.asm.load_constant(imm as u64, scratch);
self.asm.mov_rr(scratch, rd, size);
}
(RegImm::Reg(rs), RegImm::Reg(rd)) => {
(RegImm::Reg(rs), rd) => {
self.asm.mov_rr(rs, rd, size);
}
_ => Self::handle_invalid_two_form_operand_combination(src, dst),
}
}

fn cmov(&mut self, _src: Reg, _dst: Reg, _cc: CmpKind, _size: OperandSize) {
todo!()
}

fn add(&mut self, dst: RegImm, lhs: RegImm, rhs: RegImm, size: OperandSize) {
fn add(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) {
match (rhs, lhs, dst) {
(RegImm::Imm(v), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Imm(v), rn, rd) => {
let imm = match v {
I::I32(v) => v as u64,
I::I64(v) => v,
Expand All @@ -183,16 +182,15 @@ impl Masm for MacroAssembler {
self.asm.add_ir(imm, rn, rd, size);
}

(RegImm::Reg(rm), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Reg(rm), rn, rd) => {
self.asm.add_rrr(rm, rn, rd, size);
}
_ => Self::handle_invalid_three_form_operand_combination(dst, lhs, rhs),
}
}

fn sub(&mut self, dst: RegImm, lhs: RegImm, rhs: RegImm, size: OperandSize) {
fn sub(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) {
match (rhs, lhs, dst) {
(RegImm::Imm(v), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Imm(v), rn, rd) => {
let imm = match v {
I::I32(v) => v as u64,
I::I64(v) => v,
Expand All @@ -202,16 +200,15 @@ impl Masm for MacroAssembler {
self.asm.sub_ir(imm, rn, rd, size);
}

(RegImm::Reg(rm), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Reg(rm), rn, rd) => {
self.asm.sub_rrr(rm, rn, rd, size);
}
_ => Self::handle_invalid_three_form_operand_combination(dst, lhs, rhs),
}
}

fn mul(&mut self, dst: RegImm, lhs: RegImm, rhs: RegImm, size: OperandSize) {
fn mul(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) {
match (rhs, lhs, dst) {
(RegImm::Imm(v), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Imm(v), rn, rd) => {
let imm = match v {
I::I32(v) => v as u64,
I::I64(v) => v,
Expand All @@ -221,30 +218,29 @@ impl Masm for MacroAssembler {
self.asm.mul_ir(imm, rn, rd, size);
}

(RegImm::Reg(rm), RegImm::Reg(rn), RegImm::Reg(rd)) => {
(RegImm::Reg(rm), rn, rd) => {
self.asm.mul_rrr(rm, rn, rd, size);
}
_ => Self::handle_invalid_three_form_operand_combination(dst, lhs, rhs),
}
}

fn float_neg(&mut self, _dst: Reg, _src: RegImm, _size: OperandSize) {
fn float_neg(&mut self, _dst: Reg, _size: OperandSize) {
todo!()
}

fn float_abs(&mut self, _dst: Reg, _src: RegImm, _size: OperandSize) {
fn float_abs(&mut self, _dst: Reg, _size: OperandSize) {
todo!()
}

fn and(&mut self, _dst: RegImm, _lhs: RegImm, _rhs: RegImm, _size: OperandSize) {
fn and(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) {
todo!()
}

fn or(&mut self, _dst: RegImm, _lhs: RegImm, _rhs: RegImm, _size: OperandSize) {
fn or(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) {
todo!()
}

fn xor(&mut self, _dst: RegImm, _lhs: RegImm, _rhs: RegImm, _size: OperandSize) {
fn xor(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) {
todo!()
}

Expand Down Expand Up @@ -351,15 +347,4 @@ impl MacroAssembler {
let shadow_sp = regs::shadow_sp();
self.asm.mov_rr(sp, shadow_sp, OperandSize::S64);
}

fn handle_invalid_two_form_operand_combination(src: RegImm, dst: RegImm) {
panic!("Invalid operand combination; src={:?}, dst={:?}", src, dst);
}

fn handle_invalid_three_form_operand_combination(dst: RegImm, lhs: RegImm, rhs: RegImm) {
panic!(
"Invalid operand combination; dst={:?}, lhs={:?}, rhs={:?}",
dst, lhs, rhs
);
}
}
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