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…TP rank divergence in DFlash/DSpark) (sgl-project#38565) Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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…ve test_flydsl_v4nm_decode to nightly (sgl-project#47969)
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Motivation
sgl-project#35573 enabled the fused QK-norm and QK-norm+RoPE paths on ROCm, but the kernels behind them still don't build on all models.
elementwise/qknorm.cuhfails outright, anddiffusion/qknorm_rope.cuhfails for neox instantiations. Non-neox rope is the one case that already worked, which is why FLUX.2 saw the benefit of sgl-project#35573 and MiniMax H3 did not.This PR removes two dead CUDA includes in qknorm.cuh, and on ROCm pins the shuffle width to the kernel's 32-lane sub-group instead of letting HIP default it to the physical wave64. With both fixed, MiniMax-H3's QK-norm paths accept ROCm.
Without these changes neither of the kernels work on ROCm. Theser are necessary for eager / compile mode parity.
CUDA is unaffected. The shuffle change is behind
#ifndef USE_ROCMand the dropped includes were dead.Modifications
elementwise/qknorm.cuhcarriedcuda_bf16.h/cuda_fp16.has dead includes, which hipcc cannot find ("fatal error: 'cuda_bf16.h' file not found"). The file reaches the GPU only throughimpl/norm.cuhand theruntime.cuhmacro shims, both of which hipcc builds, so the includes can just go.__shfl_sync(kActiveMask, ...)passes auint32_tmask, and HIP static_assertssizeof(MaskT) == 8. On ROCm this now calls__shfl(..., partner_lane, device::kWarpThreads)instead.device::kWarpThreadsis 32u unconditionally, so the kernel indexes lanes in 32-wide logical warps, while HIP defaults the shuffle width to the physical wave64.partner_laneis an index inside that 32-lane sub-group, so the width has to be explicit.minimax_h3.py gated
_apply_qk_normand_use_fused_qknorm_ropeoncurrent_platform.is_cuda(). Both now accept ROCm, which is what reaches the two kernels above. MiniMax uses is_neox=True, the instantiation that did notbuild.
Accuracy Tests
For testing, using MiniMax-H3. The output changes slightly (exactly 1 BF16 ULP) as expected by the rope kernel. Enabling torch.compile would change it as well. No artifacts present.
Command:
Before
v0.mp4
After
pr1.mp4
Speed Tests and Profiling
1. High-level Summary
2. Stage Breakdown
Checklist
Review and Merge Process
/tag-and-rerun-ci,/tag-run-ci-label,/rerun-failed-ci