Skip to content

Conversation

@mehrdadh
Copy link
Member

@mehrdadh mehrdadh commented Sep 8, 2022

This PR adds a mechanism to overwrite device tree configs in zephyr project. It also adds an overlay for nucleo_l4r5zi board to change processor frequency from 80MHz which is the default to 120MHz.

cc @alanmacd @areusch @gromero @guberti

@github-actions github-actions bot requested review from areusch and gromero September 8, 2022 18:35
Copy link
Contributor

@areusch areusch left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks @mehrdadh

Copy link
Member

@guberti guberti left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM - thanks for this change!

@mehrdadh mehrdadh merged commit 1d32c40 into apache:main Sep 9, 2022
@mehrdadh mehrdadh deleted the micro/add_board_overlay branch September 9, 2022 16:25
@gromero
Copy link
Contributor

gromero commented Sep 9, 2022

@mehrdadh Nice findings, I wonder if you would like to upstream it to Zephyr also so other projects could pick this up?

Comment on lines +21 to +23
&rcc {
clock-frequency = <DT_FREQ_M(120)>;
};
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

That is not correct.
You should update the PLL configuration accordingly:

&pll {
	div-m = <2>;
	mul-n = <30>;
	div-p = <7>;
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_hsi>;
	status = "okay";
};

Note that the impacts of effects on bus configurations have to be tested.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@erwango Thanks a lot. Do you mind to tell how exactly one finds the params (M, N, P, Q, and R) for the PLL? I see them in the clock tree in RM0432 rev. 9 (Arm Reference Manual), Figure 16, but could not find any formula about how to relate them to the 120 MHz freq.

Copy link

@erwango erwango Sep 12, 2022

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@erwango Thanks a lot. Do you mind to tell how exactly one finds the params (M, N, P, Q, and R) for the PLL? I see them in the clock tree in RM0432 rev. 9 (Arm Reference Manual), Figure 16, but could not find any formula about how to relate them to the 120 MHz freq.

Core freq = Input freq (HSI: 16MHz) / M(2) * N(30) / R(2)

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@erwango Thanks for the explanation. I found also the formula in the Reference Manual, below the bit descriptions for the RCC_PLLCFGR, where also there are formulas using the Q and P params. Could you please review #12756 ?

@mehrdadh
Copy link
Member Author

@erwango thanks for catching this and @gromero for the follow up PR!

mkatanbaf pushed a commit to mkatanbaf/tvm that referenced this pull request Sep 14, 2022
xinetzone pushed a commit to daobook/tvm that referenced this pull request Nov 25, 2022
guberti pushed a commit that referenced this pull request Jan 13, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

5 participants