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Merge pull request torvalds#54 from HarveyHunt/ci20-v3.18-mmc-regress…
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…ion-cgu

Ci20 v3.18 MSC0 Performance Fix
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@ZubairLK
ZubairLK committed Jul 24, 2015
2 parents a19d10e + 41903f7 commit 17b6872
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Showing 5 changed files with 46 additions and 35 deletions.
2 changes: 1 addition & 1 deletion arch/mips/boot/dts/ci20.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@

&msc0 {
bus-width = <4>;
max-frequency = <48000000>;
max-frequency = <50000000>;
cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;

pinctrl-names = "default";
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24 changes: 12 additions & 12 deletions drivers/clk/jz47xx/jz4740-cgu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -94,81 +94,81 @@ static const struct jz47xx_cgu_clk_info jz4740_cgu_clocks[] = {
[JZ4740_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1 },
.div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 21, 0, 1, -1, -1, -1 },
},

[JZ4740_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1 },
.div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
.div = { CGU_REG_CPCCR, 0, 0, 4, 22, -1, -1 },
},

[JZ4740_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1 },
.div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
.div = { CGU_REG_CPCCR, 4, 0, 4, 22, -1, -1 },
},

[JZ4740_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1 },
.div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
.div = { CGU_REG_CPCCR, 8, 0, 4, 22, -1, -1 },
},

[JZ4740_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1 },
.div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 },
.div = { CGU_REG_CPCCR, 12, 0, 4, 22, -1, -1 },
},

[JZ4740_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1 },
.div = { CGU_REG_CPCCR, 16, 5, 22, -1, -1 },
.div = { CGU_REG_CPCCR, 16, 0, 5, 22, -1, -1 },
.gate_bit = 10,
},

[JZ4740_CLK_LCD_PCLK] = {
"lcd_pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL_HALF, -1 },
.div = { CGU_REG_LPCDR, 0, 11, -1, -1, -1 },
.div = { CGU_REG_LPCDR, 0, 0, 11, -1, -1, -1 },
},

[JZ4740_CLK_I2S] = {
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1 },
.mux = { CGU_REG_CPCCR, 31, 1 },
.div = { CGU_REG_I2SCDR, 0, 8, -1, -1, -1 },
.div = { CGU_REG_I2SCDR, 0, 0, 8, -1, -1, -1 },
.gate_bit = 6,
},

[JZ4740_CLK_SPI] = {
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1 },
.mux = { CGU_REG_SSICDR, 31, 1 },
.div = { CGU_REG_SSICDR, 0, 4, -1, -1, -1 },
.div = { CGU_REG_SSICDR, 0, 0, 4, -1, -1, -1 },
.gate_bit = 4,
},

[JZ4740_CLK_MMC] = {
"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1 },
.div = { CGU_REG_MSCCDR, 0, 5, -1, -1, -1 },
.div = { CGU_REG_MSCCDR, 0, 0, 5, -1, -1, -1 },
.gate_bit = 7,
},

[JZ4740_CLK_UHC] = {
"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1 },
.div = { CGU_REG_UHCCDR, 0, 4, -1, -1, -1 },
.div = { CGU_REG_UHCCDR, 0, 0, 4, -1, -1, -1 },
.gate_bit = 14,
},

[JZ4740_CLK_UDC] = {
"udc", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1 },
.mux = { CGU_REG_CPCCR, 29, 1 },
.div = { CGU_REG_CPCCR, 23, 6, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 23, 0, 6, -1, -1, -1 },
/* TODO: gate via SCR */
},

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40 changes: 20 additions & 20 deletions drivers/clk/jz47xx/jz4780-cgu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -228,21 +228,21 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
[JZ4780_CLK_CPU] = {
"cpu", CGU_CLK_DIV,
.parents = { JZ4780_CLK_CPUMUX, -1 },
.div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },
.div = { CGU_REG_CLOCKCONTROL, 0, 0, 4, 22, -1, -1 },
},

[JZ4780_CLK_L2CACHE] = {
"l2cache", CGU_CLK_DIV,
.parents = { JZ4780_CLK_CPUMUX, -1 },
.div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },
.div = { CGU_REG_CLOCKCONTROL, 4, 0, 4, -1, -1, -1 },
},

[JZ4780_CLK_AHB0] = {
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL },
.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
.div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },
.div = { CGU_REG_CLOCKCONTROL, 8, 0, 4, 21, -1, -1 },
},

[JZ4780_CLK_AHB2PMUX] = {
Expand All @@ -255,36 +255,36 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
[JZ4780_CLK_AHB2] = {
"ahb2", CGU_CLK_DIV,
.parents = { JZ4780_CLK_AHB2PMUX, -1 },
.div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },
.div = { CGU_REG_CLOCKCONTROL, 12, 0, 4, 20, -1, -1 },
},

[JZ4780_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4780_CLK_AHB2PMUX, -1 },
.div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },
.div = { CGU_REG_CLOCKCONTROL, 16, 0, 4, 20, -1, -1 },
},

[JZ4780_CLK_DDR] = {
"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
.mux = { CGU_REG_DDRCDR, 30, 2 },
.div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },
.div = { CGU_REG_DDRCDR, 0, 0, 4, 29, 28, 27 },
},

[JZ4780_CLK_VPU] = {
"vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL, -1 },
.mux = { CGU_REG_VPUCDR, 30, 2 },
.div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },
.div = { CGU_REG_VPUCDR, 0, 0, 4, 29, 28, 27 },
.gate_bit = 32 + 2,
},

[JZ4780_CLK_I2SPLL] = {
"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1 },
.mux = { CGU_REG_I2SCDR, 30, 1 },
.div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_I2SCDR, 0, 0, 8, 29, 28, 27 },
},

[JZ4780_CLK_I2S] = {
Expand All @@ -298,15 +298,15 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_VPLL, -1 },
.mux = { CGU_REG_LP0CDR, 30, 2 },
.div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },
.div = { CGU_REG_LP0CDR, 0, 0, 8, 28, 27, 26 },
},

[JZ4780_CLK_LCD1PIXCLK] = {
"lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_VPLL, -1 },
.mux = { CGU_REG_LP1CDR, 30, 2 },
.div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },
.div = { CGU_REG_LP1CDR, 0, 0, 8, 28, 27, 26 },
},

[JZ4780_CLK_MSCMUX] = {
Expand All @@ -318,21 +318,21 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
[JZ4780_CLK_MSC0] = {
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4780_CLK_MSCMUX, -1 },
.div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_MSC0CDR, 0, 1, 8, 29, 28, 27 },
.gate_bit = 3,
},

[JZ4780_CLK_MSC1] = {
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4780_CLK_MSCMUX, -1 },
.div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_MSC1CDR, 0, 1, 8, 29, 28, 27 },
.gate_bit = 11,
},

[JZ4780_CLK_MSC2] = {
"msc2", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4780_CLK_MSCMUX, -1 },
.div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_MSC2CDR, 0, 1, 8, 29, 28, 27 },
.gate_bit = 12,
},

Expand All @@ -341,15 +341,15 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
.mux = { CGU_REG_UHCCDR, 30, 2 },
.div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_UHCCDR, 0, 0, 8, 29, 28, 27 },
.gate_bit = 24,
},

[JZ4780_CLK_SSIPLL] = {
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
.mux = { CGU_REG_SSICDR, 30, 1 },
.div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },
.div = { CGU_REG_SSICDR, 0, 0, 8, 29, 28, 27 },
},

[JZ4780_CLK_SSI] = {
Expand All @@ -362,15 +362,15 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
.mux = { CGU_REG_CIMCDR, 31, 1 },
.div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },
.div = { CGU_REG_CIMCDR, 0, 0, 8, 30, 29, 28 },
},

[JZ4780_CLK_PCMPLL] = {
"pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
.mux = { CGU_REG_PCMCDR, 29, 2 },
.div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },
.div = { CGU_REG_PCMCDR, 0, 0, 8, 28, 27, 26 },
},

[JZ4780_CLK_PCM] = {
Expand All @@ -385,7 +385,7 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL },
.mux = { CGU_REG_GPUCDR, 30, 2 },
.div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },
.div = { CGU_REG_GPUCDR, 0, 0, 4, 29, 28, 27 },
.gate_bit = 32 + 4,
},

Expand All @@ -394,7 +394,7 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_VPLL, -1 },
.mux = { CGU_REG_HDMICDR, 30, 2 },
.div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },
.div = { CGU_REG_HDMICDR, 0, 0, 8, 29, 28, 26 },
.gate_bit = 32 + 9,
},

Expand All @@ -403,7 +403,7 @@ static const struct jz47xx_cgu_clk_info jz4780_cgu_clocks[] = {
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
JZ4780_CLK_EPLL },
.mux = { CGU_REG_BCHCDR, 30, 2 },
.div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },
.div = { CGU_REG_BCHCDR, 0, 0, 4, 29, 28, 27 },
.gate_bit = 1,
},

Expand Down
9 changes: 8 additions & 1 deletion drivers/clk/jz47xx/jz47xx-cgu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -332,6 +332,7 @@ static unsigned long jz47xx_clk_recalc_rate(struct clk_hw *hw,
div = (div_reg >> clk_info->div.shift) &
((1 << clk_info->div.bits) - 1);
div += 1;
div <<= clk_info->div.div;

rate /= div;
}
Expand All @@ -352,6 +353,12 @@ static unsigned jz47xx_clk_calc_div(const struct jz47xx_cgu_clk_info *clk_info,
div = min_t(unsigned, div, 1 << clk_info->div.bits);
div = max_t(unsigned, div, 1);

/* If the divider value itself must be divided before being written to
* the divider register, we must ensure we don't have any bits set that
* would be lost as a result of doing so. */
div >>= clk_info->div.div;
div <<= clk_info->div.div;

return div;
}

Expand Down Expand Up @@ -401,7 +408,7 @@ static int jz47xx_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
/* update the divide */
mask = (1 << clk_info->div.bits) - 1;
reg &= ~(mask << clk_info->div.shift);
reg |= (div - 1) << clk_info->div.shift;
reg |= ((div >> clk_info->div.div) - 1) << clk_info->div.shift;

/* clear the stop bit */
if (clk_info->div.stop_bit != -1)
Expand Down
6 changes: 5 additions & 1 deletion drivers/clk/jz47xx/jz47xx-cgu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,11 @@ struct jz47xx_cgu_mux_info {
/**
* struct jz47xx_cgu_div_info - information about a divider
* @reg: offset of the divider control register within the CGU
* @shift: number of bits to shift the divide value by (ie. the index of
* @shift: number of bits to left shift the divide value by (ie. the index of
* the lowest bit of the divide value within its control register)
* @div: number of bits to right shift the divide value by (ie. for if the
* effective divider value is the value written to the register
* multiplied by some constant).
* @bits: the size of the divide value in bits
* @ce_bit: the index of the change enable bit within reg, or -1 is there
* isn't one
Expand All @@ -91,6 +94,7 @@ struct jz47xx_cgu_mux_info {
struct jz47xx_cgu_div_info {
unsigned reg;
unsigned shift:5;
unsigned div:5;
unsigned bits:5;
int ce_bit:6;
int busy_bit:6;
Expand Down

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