MIPS: Ci20: Increase MMC0 max-frequency in DT node

The closest clockspeed to 48Mhz that the MSC supports is 50Mhz. However, as this is greater than 48Mhz the MSC clock divider is increased - causing the clock speed to become 25Mhz. Signed-off-by: Harvey Hunt <[email protected]>
aejsmith · Jul 23, 2015 · 41903f7 · 41903f7
1 parent 2976468
commit 41903f7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/arch/mips/boot/dts/ci20.dts b/arch/mips/boot/dts/ci20.dts
@@ -125,7 +125,7 @@
 
 &msc0 {
 	bus-width = <4>;
-	max-frequency = <48000000>;
+	max-frequency = <50000000>;
 	cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
 
 	pinctrl-names = "default";