Catch partial support of SVI #5422
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KrystalDelusion
changed the title
Add test to check that it does error.
Also some formatting fixes.
KrystalDelusion
changed the title
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What are the reasons/motivation for this change?
Close #5366.
The current approach to interfaces in
read_verilog -svinvolves expanding module ports to include all interface signals instead. Since this changes the number and index of ports, it is not possible to use interfaces in positional arguments (without refactoring),Explain how this is achieved.
Make sure your change comes with tests. If not possible, share how a reviewer might evaluate it.
New test added for error, current version of Yosys silently fails to match arguments post interface-expansion. Shouldn't affect any other tests.